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WO/2016/054455A1 |
Self-interference cancellers are provided. The self-interference cancellers can include multiple second-order, N-path Gm-C filters. Each filter can be configured to cancel self- interference on a channel of a desired bandwidth. Each filt...
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WO/2016/046883A1 |
A reception circuit provided with: a de-serializer that converts serial data to parallel data in accordance with a processing clock; a phase difference detection unit that detects, on the basis of the parallel data, a phase difference be...
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WO/2016/043592A1 |
A phase-domain delta-sigma (ΔΣ) modulator in a phase digitizer determines a demodulated phase error based on a phase-modulated frequency signal, in which a carrier frequency is modulated with a fundamental frequency and an associated p...
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WO/2016/044057A1 |
Some embodiments include apparatuses and methods having a digitally controlled oscillator (DCO) in a digital phase-locked loop (PLL) and a control loop. The DCO can generate an output signal having a frequency based on a value of a digit...
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WO/2016/042911A1 |
In order to reduce a leak current flowing through a charge pump circuit when charge pump operation is stopped, the present invention is provided with a plurality of charge pump circuits that each generate a charge pump current at a commo...
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WO/2016/039688A1 |
According to various embodiments, there is provided a method for generating a reference clock signal, the method including discharging a capacitive element to a discharged state, when a reset signal has a predetermined reset state; charg...
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WO/2016/036624A1 |
Embodiments are disclosed that relate to multi-phase clock generators (174, 184) and data samplers (142, 156) for use in high speed I/O circuitry (100). One disclosed example provides a multi-phase clock generator (174) including a delay...
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WO/2016/032665A1 |
Certain aspects of the present disclosure support a method and apparatus for foreground and background bandwidth calibration in a frequency-do-digital converter based phase-locked loop (FDC-PLL) device.
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WO/2016/032667A1 |
Certain aspects of the present disclosure support a method and apparatus for fast frequency throttling and re-locking in a phase-locked loop (PLL) device. Aspects of the present disclosure present a method and apparatus for operating in ...
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WO/2016/027741A1 |
Provided is a technique for suppressing the aging of oscillation frequency and obtaining a stable oscillation output in an oscillation device using a piezoelectric oscillator. In an OCXO 1 for outputting an oscillation frequency by oscil...
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WO/2016/029066A1 |
A digital signal synthesizer for generating a frequency and/or phase modified digital signal output comprises an input buffer, a transform module, a processing module, and an output buffer. The input buffer receives a digital input that ...
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WO/2016/029058A1 |
A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is ...
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WO/2016/027742A1 |
[Problem] To simplify an internal configuration to achieve low power consumption. [Solution] A wireless communication device is provided with: an analog control loop unit; a digital control loop unit; a voltage controlled oscillator for ...
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WO/2016/027945A1 |
The present invention provides a phase locked loop apparatus having multiple negative feedback loops, comprising: a first negative feedback loop for comparing a reference signal with a divided signal of an output signal output from a vol...
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WO/2016/026667A1 |
A circuit arrangement for clock and data recovery comprises a control unit (CTRL), a phase-locked loop circuit (PLL) and a sampling unit (SMPL). The control unit (CTRL) is configured to derive a first reference signal (PLSN) and a second...
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WO/2016/021840A1 |
A delay synchronization loop according to the present invention includes a voltage control delay line and a phase detector, the phase detector (100) comprising: a sampler unit (120) for sampling a data signal on the basis of a clock, the...
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WO/2016/015931A1 |
Systems and methods for compensating for a known interferer to a Controlled Oscillator (CO) of a Phase-Locked Loop (PLL) are disclosed. In one embodiment, a system includes a PLL and a compensation system. The compensation system is conf...
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WO/2016/015673A1 |
A loop filter has a first switched-capacitor network and a second switched-capacitor network. The first switched-capacitor network is coupled to an input node of the loop filter. The second switched-capacitor network is coupled to the in...
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WO/2016/011635A1 |
A voltage controlled oscillator (VCO) is disclosed. The VCO includes an amplifier that receives a control signal and a feedback signal and generates an amplified output signal based on the difference between the control signal and the fe...
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WO/2016/012035A1 |
The invention relates to an apparatus (100) for synchronizing a sampling signal on a communication signal, the communication signal comprising communication symbols, the sampling signal indicating sampling time instants of the communicat...
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WO/2016/012036A1 |
A timing recovery apparatus for receivers is disclosed. The apparatus includes a feedback loop with two parallel branches, each branch having an interpolation filter and a phase detector. The feedback loop additionally includes a combine...
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WO/2016/008362A1 |
A direct digital synthesizing method, comprising the following steps: a phase accumulation module calculates based on a frequency synthesizing word and obtains a first phase (S101); searching a preset sine lookup table for an amplitude v...
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WO/2016/010629A1 |
A clock synchronization circuit includes a multi-phase clock generator to generate a plurality of delayed clocks, each delayed clock having a unique delay with regard to a source clock. The clock synchronization circuit further includes ...
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WO/2016/003682A1 |
An automatic test system configured for generating a periodic signal of a programmable frequency. The automatic test system may comprise a clock, an edge generator coupled to the clock, a phase locked loop, and a delay adjustment circuit...
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WO/2015/196349A1 |
A multi-standard performance reconfigurable I/Q quadrature carrier generator. By means of reasonable frequency assignment, 0.1-5GHz continuously covered I/Q carrier output as well as 5-10GHz and 1.5-3GHz continuously covered differential...
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WO/2015/196406A1 |
Disclosed in the present invention is a wireless radio frequency transmission device. The wireless radio frequency transmission device comprises a phase frequency detector, a charge pump, a loop filter and a twin voltage controlled oscil...
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WO/2015/199068A1 |
To provide a technique with which it is possible, in an oscillation device, to minimize fluctuations in oscillation frequency caused by fluctuations in the voltage of a power supply unit of a heater. An oscillation device in which the te...
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WO/2015/196181A1 |
An integrated circuit implements at least part of a phase locked loop (PLL). The integrated circuit includes a sampled analog loop filter for the PLL. The loop filter includes a first input for receiving a signal representative of a phas...
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WO/2015/189151A1 |
A power transmission network comprises: an AC electrical network connected to a point of common coupling, the point of common coupling being connectable to a further electrical device; a processing circuit configured to receive and proce...
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WO/2015/191000A1 |
According to embodiments of the present invention, an oscillator is provided. The oscillator includes a switched capacitor circuit arrangement configured to generate a predetermined voltage, a transconductance-capacitor filter configured...
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WO/2015/191483A1 |
A data lock detection system may include a receiver configured to receive a data signal, a phase detector configured to output a phase detection output signal representative of the data signal with respect to a clock signal, and a lock d...
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WO/2015/191235A1 |
A memory controller is provided that drives data and a corresponding first data strobe to a plurality of endpoints. Each endpoint is configured to register the received data from the memory controller responsive to the first data strobe ...
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WO/2015/184963A1 |
A phase-locked loop frequency correction method and system are applied to selection of sub-bands of a multi-band voltage-controlled oscillator. The method comprises: within counting time TCNT[k], performing frequency counting on a freque...
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WO/2015/187308A1 |
Systems and methods for delay control are described herein. In one embodiment, a delay system comprises a first delay circuit configured to provide a voltage bias to a second delay circuit, wherein the voltage bias controls a delay of th...
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WO/2015/183341A1 |
Systems, methods, and devices are disclosed for implementing frequency calibration circuits. The devices may include a data source configured to generate a first data signal based on a first data value and a second data signal based on a...
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WO/2015/183584A1 |
Aspects of a reconfigurable frequency divider circuit are provided. A reconfigurable frequency divider can include a frequency divider that is configured to receive an input signal. The frequency divider can also include a delay circuit ...
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WO/2015/177200A1 |
A digital phase lock loop circuit includes a phase detector, loop filter, finite impulse response filter (FIR), a plurality of digital to analog converters (DACs), a voltage controlled oscillator (VCO), and a divider. The FIR filter incl...
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WO/2015/172372A1 |
A fractional-N phase locked loop (PLL) circuit (104, 600, 800) is provided. The PLL circuit (104, 600, 800) generates a spread spectrum clock (SSC), using average techniques to suppress phase interpolator nonlinearity. The PLL circuit (6...
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WO/2015/172481A1 |
A device and method for setting the signal frequency of a timing sequence controller (TCON) of a display device; the device comprises a frequency setting module for setting the signal frequency of the TCON of the display device as a fixe...
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WO/2015/171265A1 |
Clock skew management systems are disclosed. Methods and related components are also disclosed. In an exemplary aspect, to offset the skew that may result across the tiers in the clock tree, a cross-tier clock balancing scheme makes use ...
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WO/2015/165829A1 |
Systems and methods for mitigating interference in a Local Oscillator (LO) signal generated by a Phase-Locked Loop (PLL) are disclosed. In one embodiment, a system includes a PLL and an error compensation subsystem. The PLL includes a Co...
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WO/2015/167805A1 |
Aspects of circuits and methods for generating an oscillating signal are disclosed. The circuit includes a phase detector configured to output first and second signals responsive to a phase difference between two input signals. The phase...
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WO/2015/167680A1 |
Systems and methods for recovering clock and data from a data input signal are disclosed that sample a plurality of clock phase signals with the data input signal to determine a timing relationship between the data input signal and the c...
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WO/2015/167109A1 |
The present invention relates to a phase locked loop device having a plurality of negative feedback loops, which comprises two negative feedback loops for locking a frequency and a phase of an output signal output from a voltage control ...
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WO/2015/161640A1 |
Provided is a time-to-digital converter, comprising a delay unit, a first sampling unit and a second sampling unit, wherein the delay unit is connected to the first sampling unit and is used for receiving a first clock signal and delayin...
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WO/2015/162055A1 |
Systems and methods for mitigating crosstalk between controlled oscillators of Phase-Locked Loops (PLLs) are disclosed. In one embodiment, a system includes a first PLL including a first controlled oscillator and a second PLL. The system...
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WO/2015/162691A1 |
This digital analog converter comprises multiple rows of ΔΣ modulation circuits and a serializer which switches between outputting output signals of the multiple ΔΣ modulation circuits. The ΔΣ modulation circuits include an integra...
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WO/2015/160344A1 |
In some examples, a circuit is described. The circuit may be included in a digital phase-locked loop (PLL) and may include a first delay cell, a second delay cell, and a delay controller. The first delay cell may include a first inverter...
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WO/2015/156089A1 |
Provided is a reception apparatus that can shorten a time in which, after temporary noise superimpositions on a digital signal become nonexistent, the original data and clocks become able to be restored from the digital signal. The recep...
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WO/2015/156077A1 |
A receiving device (20) is provided with a voltage controlled oscillator (22), a sampling unit (23), a control-voltage-generating unit (24), a fault-detecting unit (25), and a control-voltage-maintaining unit (26). The control-voltage-ma...
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