| Document |
Document Title |
|
JP2022185856A |
To provide a semiconductor storage device capable of increasing a heating temperature in a memory cell, improving locality of a heat generation position, and reducing disturbance (data corruption) to an adjacent memory cell.A semiconduct...
|
|
JP2022552202A |
TECHNICAL FIELD The disclosed technology relates generally to barrier layers comprising titanium silicon nitride, and more particularly to barrier layers for non-volatile memory devices and methods of forming the same. In one aspect, a m...
|
|
JP2022181756A |
To provide a semiconductor storage device capable of achieving lower power and higher integration.A non-volatile semiconductor memory 100 includes a memory cell array 110 in which a NOR-type array 110A having a NOR-type flash memory stru...
|
|
JP7175896B2 |
A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surro...
|
|
JP7170931B2 |
Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or ...
|
|
JP7165976B2 |
To stabilize programming operation and to reduce leakage current. A variable resistance element according to the present invention is provided with: an interlayer insulating film; a first electrode that is formed within the interlayer in...
|
|
JP7166363B2 |
Methods, systems, and devices for fabrication of memory cells are described. An electrode layer may have an initial thickness variation after being formed. The electrode layer may be smoothened prior to forming additional layers of a mem...
|
|
JP2022544497A |
Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include a layered assembly of materials including a first conductive material and a first sacrificial material to form a first...
|
|
JP7155752B2 |
A resistance change device includes a first resistance change layer that occludes and discharges ions of at least one type, and resistance of the first resistance change layer, changes in accordance with an amount of the ions in such a m...
|
|
JP2022152035A |
To provide a memory cell capable of achieving multilevel storage with a simple configuration and at low cost, and a storage method using the same.A memory cell includes a first electrode layer and a second electrode layer, and a solid el...
|
|
JP2022542744A |
A method for controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film containing intrinsic defects on a substrate, forming a plasma-enhanced...
|
|
JP2022147118A |
To provide a nonvolatile storage device capable of reducing a leakage current flowing in a switch layer, stabilizing information reading operation, and realizing an increased storage capacity.A nonvolatile storage device includes a first...
|
|
JP2022147390A |
To provide a storage device including a resistance change memory element having excellent performance.A storage device according to an embodiment includes a resistance change memory element 140 including a first electrode 141, a second e...
|
|
JP2022146047A |
To provide a selector device capable of enhancing the heat confinement effect of a selector layer and improving the characteristics.A selector device 1 according to an embodiment includes a first electrode 2, a second electrode 3, and a ...
|
|
JP2022144071A |
To provide a variable-resistance element and a memory device, which enable the achievement of higher speed of crystallization of a resistance-changing layer, and low power consumption.A variable-resistance element 1 according to an embod...
|
|
JP2022144045A |
To provide a selector device with an improved cycle characteristic.A selector device 1 according to this embodiment includes a first electrode 2, a second electrode 3, a selector layer 4 disposed between the first electrode 2 and the sec...
|
|
JP7145495B2 |
To achieve both functions of a memory element and a selector element in a laminated structure of amorphous oxides arranged between a first metal electrode and a second metal electrode.A nonvolatile memory element 10 according to the pres...
|
|
JP2022143783A |
To provide a semiconductor storage device capable of improving electric characteristics, and a method for manufacturing the semiconductor storage device.A semiconductor storage device of an embodiment comprises a first wiring, a second w...
|
|
JP2022142228A |
To provide a semiconductor storage device with improved durability.A semiconductor storage device configured as a non-volatile storage device which uses a ferroelectric layer comprises a channel layer 120 containing titanium oxide. an el...
|
|
JP2022142627A |
To provide a semiconductor storage device capable of suppressing a reset current.A semiconductor storage device according to an embodiment includes an electrode made of a first material, further includes a memory material made of a secon...
|
|
JP2022541886A |
Embodiments of the present invention relate to forming substoichiometric metal oxide films using a modified atomic layer deposition (ALD) process. In a non-limiting embodiment of the invention, a first precursor and a second precursor ar...
|
|
JP7140476B2 |
An aluminum compound is represented by Chemical Formula (I) and is used as a source material for forming an aluminum-containing thin film.
|
|
JP2022540786A |
A method, system, and apparatus are described for a memory device having a split pillar architecture. The memory device has a pattern of conductive contacts and openings through alternating layers of conductive and insulating materials t...
|
|
JP7138722B2 |
Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cro...
|
|
JP7137615B2 |
A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certa...
|
|
JP2022539459A |
A method for producing stable strontium titanate nanocube sols is disclosed. The sol is useful for fabricating switchable layers suitable for RRAM applications, and the switching performance is stable and reproducible. The RRAM layer con...
|
|
JP2022125684A |
To provide a resistance change type storage device in which disturbance can be suppressed and high integration is possible.A resistance change type storage device according to one embodiment includes a memory cell, a first conductor, a s...
|
|
JP7124059B2 |
A semiconductor device is disclosed. The semiconductor device includes a transistor including a source contact, a drain contact, and a channel region including an oxide semiconductor material as the channel material. At least one of the ...
|
|
JP7123151B2 |
Methods and devices based on the use of dopant-modulated etching are described. During fabrication, a memory storage element of a memory cell may be non-uniformly doped with a dopant that affects a subsequent etching rate of the memory s...
|
|
JP7116498B2 |
Provided are a layered compound having indium and arsenic, a nanosheet that may be prepared using the same, and an electrical device including the materials. Provided is a layered compound represented by [Formula 1] Na1-xInyAsz (0≤x<1....
|
|
JP2022117470A |
To provide a variable resistance memory element.A variable resistance memory element includes: a support layer made of an insulating material; a variable resistance layer arranged on the support layer and containing a variable resistance...
|
|
JP7116377B2 |
Memristive devices based on ion-transfer between two meta-stable phases in an ion intercalated material are provided. In one aspect, a memristive device is provided. The memristive device includes: a first inert metal contact; a layer of...
|
|
JP7116499B2 |
Provided are a layered compound having indium and phosphide, a nanosheet that may be prepared using the same, and an electrical device including the materials. Provided is a layered compound represented by K1-xInyPz (0≤x≤1.0, 0.75≤...
|
|
JP7116785B2 |
Numerous embodiments of circuitry for a set-while-verify operation and a reset-while verify operation for resistive random access memory cells are disclosed. In one embodiment, a set-while-verify circuit for performing a set operation on...
|
|
JP2022116167A |
To provide a memory element including a phase-change material having a larger band gap and a larger SET speed according to an embodiment.Methods, systems, and devices for operating memory cell(s) using transition metal-doped GST are desc...
|
|
JP7116156B2 |
A self-selecting memory cell may be composed of a memory material that changes threshold voltages based on the polarity of the voltage applied across it. Such a memory cell may be formed at the intersection of a conductive pillar and ele...
|
|
JP2022113999A |
To provide a semiconductor storage device that operates favorably.A semiconductor storage device includes: a substrate; a first conductive layer spaced from the substrate in a first direction and extending in a second direction; a second...
|
|
JP2022112985A |
To provide a nonvolatile storage device capable of realizing high performance.A nonvolatile storage device comprises a first electrode, a memory material layer, a second electrode, and a first buffer layer. The memory material layer incl...
|
|
JP2022112884A |
To provide a semiconductor storage device capable of being easily miniaturized.A semiconductor storage device comprises first and second electrodes, a phase change layer provided between the first and second electrodes, and a first layer...
|
|
JP2022111856A |
To provide a switch element and a memory device capable of improving integration efficiency of a memory cell.A switch element according to an embodiment of the present disclosure includes a first electrode, a second electrode arranged to...
|
|
JP2022107072A |
To provide a new variable resistance device with a variable resistance state.One typical variable resistance device of the present invention includes an organic film and first and second electrodes at least portions of which are opposing...
|
|
JP2022532554A |
The present invention is in formula I D1-ZD-(A1-Z1)r-B1-(Z2-A2)s-Sp-G (I) Here, the groups and parameters that occur have the meaning given in claim 1. In the diamondoid compound represented by, its use for the formation of molecular lay...
|
|
JP2022532553A |
In the present invention, the formula I: R1-(A1-Z1)r-B1-ZL-A2-(Z3-A3)s-The compound represented by G (I), in which the groups and parameters appearing in the formula have the meaning given in claim 1, for the formation of a molecular lay...
|
|
JP7097599B2 |
To provide: a phase change material having a novel composition suitable for achieving a phase change type memory element superior in practicability; and a phase change type memory element arranged by use of the phase change material.A ph...
|
|
JP7096710B2 |
A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; and a second memory section laterally spaced apart...
|
|
JP2022099300A |
To provide a technology of designing and producing an RPU in which drift is reduced.There is provided a tunable nonvolatile resistive element in which a device conductance is modulated by changing the length of a contact between a phase ...
|
|
JP2022096635A |
To provide an efficient voltage resistance controlling apparatus for controlling voltage resistance.A computer system is connected to a voltage resistance controlling apparatus that includes: at least two electrodes 202 and 204 on proxim...
|
|
JP2022092569A |
To provide a memory device structure, a method of fabricating a deck select transistor, and a system, which increase the memory density while minimizing the decoder transistor footprint.A memory device structure 100 includes first line s...
|
|
JP2022092570A |
To provide a pillar select transistor which increases the memory density while minimizing the decoder transistor footprint in a cross point memory array.A memory device structure 100 includes a vertical pillar select transistor 102 havin...
|
|
JP2022091726A |
To solve the problem in which resistive random-access memory (ReRAM) memory is integrated in a higher level of BEOL interconnect and it is desired to incorporate the ReRAM into a lower BEOL level.A cross-bar resistive random-access memor...
|
