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Patent Searching and Data


Matches 351 - 400 out of 857,845

Document Document Title
WO/2019/051354A1
Systems and methods are provided for reducing power in in-memory computing, matrix-vector computations, and neural networks. An apparatus for in-memory computing using charge-domain circuit operation includes transistors configured as me...  
WO/2019/049980A1
In order to achieve both high-density implementation of applications in the form a reconfiguration circuit without a redundancy bit and the capability to continuously run applications with redundancy, the present invention is a reconfigu...  
WO/2019/050867A1
Apparatuses and methods are disclosed for detecting a loop count in a delay-locked loop that uses a divide clock in a measure initialization process. An example apparatus includes a divider configured to receive a signal and produce a fi...  
WO/2019/050625A1
Numerous embodiments of circuitry for writing to and reading from resistive random access memory cells are disclosed. Various architectures and layouts for an array of resistive access memory cells also are disclosed.  
WO/2019/050117A1
The present invention relates to a device and a method for producing a multimedia book. The present invention provides a device and a method for producing multimedia book content, whereby recorded data for content on the respective pages...  
WO/2019/048967A1
Provided is a storage device in which the parasitic capacitance of a bit line has been reduced. The storage device comprises a sense amplifier that is electrically connected to a bit line, and a memory cell array that is layered upon the...  
WO/2019/049842A1
Provided is a neural network computation circuit capable of outputting output data according to the result of a multiply-accumulate operation performed on input data and connection weight coefficients, said circuit comprising a computati...  
WO/2019/049585A1
Provided is a fluorinated ether compound represented by formula (1). (1): R1-R2-CH2-R3-CH2-R4 (In the formula (1), R1 is an alkyl group optionally having a substituent, R2 is a divalent linking group linked to R1 via etheric oxygen, R3 i...  
WO/2019/048979A1
Provided is electronic equipment having a semiconductor device capable of intermittent operation. The electronic equipment has a semiconductor device, and the semiconductor device has a current mirror circuit, a bias circuit and first th...  
WO/2019/049013A1
Provided is a novel semiconductor device. The semiconductor device comprises a plurality of cell arrays and a plurality of peripheral circuits, wherein each cell array has a plurality of memory cells; each peripheral circuit has a first ...  
WO/2019/051446A1
Multi-pump memory system access circuits for sequentially executing parallel memory operations in a memory system are disclosed. A memory system includes a plurality of memory bit cells in a memory array. Each memory bit cell is accessib...  
WO/2019/049654A1
A neural network computation circuit comprising an in-area word line multiple selection circuit for logically segmenting a plurality of word lines of a memory array (10) into a plurality of word line areas and making a given word line se...  
WO/2019/045921A1
Methods of operating memory, and apparatus configured to perform similar methods, include obtaining information indicative of a data value stored in a particular memory cell of the memory, programming additional data to the particular me...  
WO/2019/045793A1
A system includes first and second sets of memory banks that store data. The system also includes an address path coupled to the memory banks that provides a row address to the memory banks. The system further includes a command address ...  
WO/2019/045682A1
Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electr...  
WO/2019/042173A1
A shift register unit and a driving method thereof, an array substrate, and a display device in the field of displays. The shift register unit comprises: a shift register module (11) configured to provide a signal at a first scan output ...  
WO/2019/045792A1
A memory device (10) may include one or more memory banks (12) that store data and one or more input buffers (50). The input buffers (50) may receive command address signals to access the one or more memory banks (12). The memory device ...  
WO/2019/044156A1
Provided is an information processing system that reproduces a write to a notebook together with the state of being written to the notebook and thereby facilitates understanding of the written content of the notebook. For this purpose, a...  
WO/2019/042189A1
A shift register circuit, a driving method, a gate drive circuit, and a display device are provided. The shift register circuit comprises a clock signal adjustment circuit (13) and a self-controlled conduction circuit (14). The clock sig...  
WO/2019/045937A1
Devices and techniques for increased NAND performance under high thermal conditions are disclosed herein. An indicator of a high-temperature thermal condition for a NAND device may be obtained. A workload of the NAND device may be measur...  
WO/2019/046524A1
Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is received. The write operation is then performed on a NAND cell using a modifi...  
WO/2019/046050A1
Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a tr...  
WO/2019/044021A1
The imaging device (100) is provided with: a selector (115, 120) for selecting sound signals for a preset number of channels; and a control unit. During recording of the sound signals, when the number of channels is set to two, the contr...  
WO/2019/041827A1
A shift register unit for a gate driver circuit (GOA), a gate driver circuit comprising the shift register unit, and a driving method applied to the shift register unit. The shift register unit comprises: an input sub-circuit (110), conf...  
WO/2019/046084A1
Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the eras...  
WO/2019/045906A1
An electronic device includes a reconfigurable charge pump including pump units that can be arranged differently for varying an output voltage generated by the reconfigurable charge pump; a pump regulator coupled to the reconfigurable ch...  
WO/2019/046032A1
Apparatuses and methods are provided for processing in memory. An example apparatus comprises a host and a processing in memory (PIM) capable device coupled to the host via an interface comprising a sideband channel. The PIM capable devi...  
WO/2019/046105A1
Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a sign...  
WO/2019/046051A1
Apparatuses and methods for memory that includes a first memory cell including a storage component having a first end coupled to a plate line and a second end coupled to a digit line, and a second memory cell including a storage componen...  
WO/2019/044061A1
To perform power-supply voltage control suited to the internal state of a memory. This memory controller is provided with a memory interface and a control unit. The memory interface is an interface for connection to the memory. The contr...  
WO/2019/046548A1
Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceed...  
WO/2019/046835A1
A three-dimensional (3D) ultra-low power neuromorphic accelerator is described. The 3D ultra-low power neuromorphic accelerator includes a power manager as well as multiple tiers. The 3D ultra-low power neuromorphic accelerator also incl...  
WO/2019/043989A1
A recording method comprises: acquiring a video stream including an independently decodable picture (S21); recording the acquired video stream onto a recording medium (S22); storing a value representing the data size of the picture in a ...  
WO/2019/046326A1
Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, ...  
WO/2019/046370A1
Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND...  
WO/2019/041840A1
A memory unit and a static random access memory. The memory unit comprises : a latch, the latch providing a first memory bit; and the memory unit further comprises a first MOS tube; the gate electrode of the first MOS tube is connected t...  
WO/2019/046104A1
Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time ...  
WO/2019/045951A1
Techniques for flash memory with row redundancy are described herein. In an example embodiment, a semiconductor device comprises an embedded flash memory. The embedded flash memory comprises a memory bank that includes multiple physical ...  
WO/2019/045796A1
The systems and methods (120) provided herein identify a command acquisition mode from a plurality of command acquisition modes of a command interface (14) of a memory device (10). A state of a chip select signal (CS) is identified. When...  
WO/2019/041291A1
Provided is an information writing method (200) applicable to an NVDIMM comprising an NVDIMM controller and an NVM. The method (200) comprises: an NVDIMM controller receiving a purge command from a host, the purge command being used to c...  
WO/2019/045973A1
Providing zero-overhead frame synchronization using synchronization strobe polarity for SOUNDWIRE Extension buses is disclosed. In one aspect, a downstream-facing interface (DFI) device determines a polarity of a next synchronization str...  
WO/2019/045882A1
In some embodiments, memory circuitry comprises a pair of immediately-adjacent memory arrays having space laterally there-between. The memory arrays individually comprise memory cells individually having upper and lower elevationally-ext...  
WO/2019/041082A1
Methods include programming a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the...  
WO/2019/046230A1
Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one ...  
WO/2019/046044A1
Devices and techniques to reduce corruption of preloaded data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, up to a threshold amount on a memory array in a ...  
WO/2019/045922A1
Methods of operating apparatus, and apparatus configured to perform similar methods, include obtaining information indicative of a data value stored in a particular memory cell of an array of volatile memory cells of the apparatus, deter...  
WO/2019/041586A1
A scanning driving circuit and a liquid crystal display. The scanning driving circuit comprises a plurality of cascaded GOA units. Each GOA unit comprises a pull-up circuit (20), a control circuit (10), a transfer circuit (30), a pull-do...  
WO/2019/046065A1
The present disclosure relates to methods and apparatus for processing media content having video content and associated audio content. A method of processing media content having video content and associated audio content comprises the ...  
WO/2019/043719A1
A system for exchanging multimedia content between a guide to a plurality of travelers comprises: a guide mobile device configured for transmitting said voice and video content from said guide, a plurality of traveler mobile devices conf...  
WO/2019/045786A1
A memory device includes a data path having a data bus. The memory derive further includes a first one-hot communications interface communicatively coupled to the data bus, and a second one-hot communications interface communicatively co...  

Matches 351 - 400 out of 857,845