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WO/2024/051072A1 |
A semiconductor processing apparatus and method. The method comprises: placing a second chamber portion at an open position relative to a first chamber portion; placing a semiconductor wafer to be processed between the first chamber port...
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WO/2024/052045A1 |
The invention relates to a susceptor for a device for depositing a layer of semiconductor material on a substrate wafer (40) by means of deposition from the gas phase, the susceptor comprising a susceptor plate and at least one substrate...
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WO/2024/054065A1 |
The present invention relates to a shielding compound, a thin film formation method using same, and a semiconductor substrate and a semiconductor device manufactured therefrom, and provides, as a shielding compound, a compound having a p...
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WO/2024/053420A1 |
This semiconductor package comprises: a plurality of semiconductor elements (1); a plurality of plate-shaped bridging members (5) that are connected to different semiconductor elements; a lead frame (2) having a plurality of mounting par...
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WO/2024/054977A1 |
Exemplary semiconductor processing methods may include providing one or more deposition precursors to a processing region of a semiconductor processing chamber. The methods may include contacting a substrate housed in the processing regi...
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WO/2024/052128A1 |
Proposed is an electronics module (100), in particular a power electronics module, comprising - a metal-ceramic substrate (1) which serves as a carrier and has a ceramic element (10) and a primary component metallization (21) and prefera...
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WO/2024/053457A1 |
Provided is a semiconductor device comprising: a gate electrode layer embedded in a gate trench; a contact trench including a first intersecting region intersecting the gate trench; and an emitter contact electrode layer embedded in the ...
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WO/2024/052291A1 |
The invention relates to a transfer stamp for transferring an optoelectronic component which comprises a stamp body (10) that has a height and a stamp surface (11) with an edge length, wherein a ratio of the height to the edge length is ...
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WO/2024/053232A1 |
This laminated film comprises in the order given: an adhesive layer containing a thermoplastic resin, a thermosetting resin, a curing agent, and a flux compound having two carboxyl groups; a pressure-sensitive adhesive layer; and a base ...
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WO/2024/050951A1 |
The present disclosure relates to a semiconductor structure and a method for forming same. The method for forming the semiconductor structure comprises the following steps: providing an initial substrate; etching the initial substrate to...
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WO/2024/053456A1 |
Provided is a semiconductor device including: a gate electrode embedded in a gate trench; a surface insulating layer that is formed on a first principal surface and that has a contact hole; a covering insulating layer that covers the gat...
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WO/2024/051124A1 |
Provided in the present invention is a multi-layer high bandwidth memory. A high bandwidth memory and a logic chip are integrated on a wafer using a fan-out embedded component packaging method, thereby improving the storage capacity; and...
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WO/2024/054344A1 |
A gas cooling cover for an exhaust connector of a substrate processing system includes a first cover portion configured for arrangement around a first portion of the exhaust connector of the substrate processing system and including a fi...
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WO/2024/051166A1 |
The present application provides a semiconductor device and a fabrication method therefor, and relates to the technical field of semiconductors. The method comprises: first providing a wide-band-gap substrate; then forming a wide-band-ga...
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WO/2024/053386A1 |
Provided is a substrate treatment system comprising: a treatment device that subjects a substrate to a treatment; a vacuum conveyance device that is connected to the treatment device via an irradiation section and has a conveyance mechan...
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WO/2024/052777A1 |
A semiconductor device, such as an integrated circuit, microprocessor, wafer, or the like, includes a first gate all around field effect transistor (GAA FET) (303) and second GAA FET (313, 323, 333) within the same region type (e.g., p-t...
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WO/2024/052619A1 |
The invention relates to a method for conditioning a composite structure comprising a thin layer of monocrystalline silicon carbide (11) disposed on a polycrystalline silicon carbide carrier substrate, the composite structure having a fr...
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WO/2024/054388A1 |
Methods and systems for performing model-less measurements of semiconductor structures based on scatterometry measurement data are described herein. Scatterometry measurement data is processed directly, without the use of a traditional m...
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WO/2024/050887A1 |
Provided in the embodiments of the present application are a wafer-cassette bearing device and a wafer processing system. A wafer cassette comprises two wafer cassette pieces arranged opposite each other, wherein each wafer cassette piec...
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WO/2024/053497A1 |
A semiconductor device according to one embodiment of the present disclosure comprises: a semiconductor substrate having a first insulating layer and a plurality of first terminals provided in the first insulating layer; and semiconducto...
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WO/2024/051061A1 |
The present disclosure relates to a semiconductor structure and a forming method therefor. The forming method for the semiconductor structure comprises the following steps: providing an initial substrate; etching the initial substrate to...
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WO/2024/051134A1 |
The present invention relates to the technical field of semiconductors. A cleaning method for improving an epitaxial stacking fault is characterized in cleaning a cleaning machine. A primary deionized water tank, a primary reagent tank, ...
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WO/2024/054311A1 |
Various embodiments of methods are provided for forming a moisture barrier layer on an EUV-active photoresist film before patterning the EUV-active photoresist film with EUV lithography. According to one embodiment, the methods disclosed...
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WO/2024/054537A1 |
A method and apparatus for performing post-exposure bake operations is described herein. After exposure of photoresist on a substrate, the substrate is heated during a baking process to facilitate protection of the resist. The baking pro...
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WO/2024/050881A1 |
The present application discloses a guide apparatus, which is used for guiding an accelerator into an ion implanter. The guide apparatus comprises: a guide plate, comprising a bearing surface and a back surface which are arranged in the ...
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WO/2024/053372A1 |
The present disclosure relates to a solid-state imaging element and a manufacturing method, and an electronic device that enable a higher image quality to be achieved. The solid-state imaging element comprises: a plurality of pixels; a c...
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WO/2024/051635A1 |
The present invention relates to an HEMT device, comprising: a two-dimensional electron gas structure and at least one pair of dual gates, wherein a two-dimensional electron gas channel is formed in the two-dimensional electron gas struc...
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WO/2024/054380A1 |
Methods and apparatus for multi-sensor determination of a state of semiconductor equipment are provided In some embodiments disclosed herein, semiconductor manufacturing equipment may include: a plurality of sensors comprising one or mor...
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WO/2024/053221A1 |
[Problem] To provide an information processing device that enables the appropriate prediction of the effect of electromagnetic waves generated from an AC power line when substrate treatment is performed. [Solution] An information process...
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WO/2024/052772A1 |
The present invention provides a semiconductor device with stable operation. This semiconductor device has a first transistor, a second transistor, a third transistor, and a first capacitance element. One among the source and drain of th...
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WO/2024/050877A1 |
Embodiments of the present application provide a laser angle assisted adjustment device for manufacturing a semiconductor. The device comprises a housing and an optical assembly. The housing is provided with an accommodation space, and t...
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WO/2024/050889A1 |
A positioning jig, which is used for assisting in mounting positioning pins on a chuck. The positioning jig comprises: a body (21), which comprises a first surface (211) and a second surface (212) arranged opposite each other in a first ...
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WO/2024/050727A1 |
A nitride-based wafer CVD device comprises a heat carrier, a nitride-based wafer, and a clamping ring. The heat carrier comprises a carrier surface. The nitride-based wafer is disposed on the carrier surface. The clamping ring is dispose...
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WO/2024/050865A1 |
Disclosed in the present invention are a vertical gallium oxide transistor and a preparation method therefor in the technical field of semiconductors. The method comprises the following steps: annealing a gallium oxide material in an oxy...
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WO/2024/053490A1 |
The present invention addresses the problem of providing a resin composition for a dicing film substrate, the resin composition being capable of forming a dicing film substrate having excellent elongation at room temperature and at low t...
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WO/2024/054716A1 |
A package comprising an integrated device and a substrate coupled to the integrated device. The substrate comprises at least one dielectric layer and a plurality of interconnects. The plurality of interconnects include a plurality of pos...
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WO/2024/054362A1 |
A method of semiconductor device microfabrication. The method includes forming, over a hardmask layer and an underlying layer, a first trench pattern between adjacent template lines that include mandrels with sidewall spacers. The first ...
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WO/2024/051021A1 |
The present invention relates to the field of chip loading. Disclosed are a tray structure and a rubber coating process for a tray structure. The tray structure comprises: a tray body; a first frame and a second frame respectively provid...
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WO/2024/053140A1 |
The present invention comprises: a first step for heating a treatment container at a predetermined heat gradient without having a treatment substrate included in the treatment container; and a second step for, after the first step, treat...
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WO/2024/054002A1 |
The technical idea of the present invention provides a semiconductor package manufacturing method comprising: a step of separating a plurality of dies from each other in the horizontal direction and arranging same on a carrier; a first s...
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WO/2024/052967A1 |
Disclosed is a method for manufacturing a semiconductor device. This method for manufacturing a semiconductor device comprises the steps for: preparing a structure that has an interposer that including a first main surface and a second m...
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WO/2024/052749A1 |
A semiconductor structure having improved performance is provided that includes a local enlarged via-to-backside power rail (VBPR) contact structure which connects a source/drain region of one field effect transistor (FET) to a backside ...
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WO/2024/051135A1 |
A method for improving a silicon-wafer cleaning effect. The method is characterized by comprising the following steps: step I, a pre-cleaned silicon wafer being put into a first feeding tank (1), wherein the silicon wafer is immersed und...
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WO/2024/051225A1 |
The present disclosure provides a fan-out system-in-package structure and a manufacturing method therefor. The method comprises: providing a support carrier; forming a first rewiring layer, a metal connection column, and a second rewirin...
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WO/2024/053832A1 |
According to one embodiment of the present invention, a method for processing substrates through a heater that heats the substrates so as to perform a semiconductor process comprises the steps of: inputting, into a correlation of the mea...
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WO/2024/052643A1 |
A lateral silicon carbide power semiconductor device (31; 101; 141; 161; 181) is disclosed. The device comprises a substrate (102) and a silicon carbide semiconductor structure (105) disposed on the substrate and having a principal surfa...
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WO/2024/053659A1 |
One aspect of the present invention provides a production method for an etching liquid composition that makes it possible to suppress dripping when a container is filled. One aspect of the present disclosure relates to a production met...
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WO/2024/053647A1 |
One embodiment of the present invention provides a post-etching substrate processing method wherein a generated water-insoluble material can be dissolved. One embodiment of the present disclosure relates to a substrate processing metho...
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WO/2024/051237A1 |
Provided in the present invention are a chip packaging structure and a preparation method therefor. The packaging structure comprises a substrate, a first redistribution layer, first chips, virtual silicon wafers, a plastic packaging lay...
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WO/2024/050914A1 |
The present disclosure relates to a semiconductor structure and a preparation method therefor. The preparation method for a semiconductor comprises: providing a substrate, and forming a semiconductor contact layer on the substrate; formi...
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