| Document |
Document Title |
|
WO/2024/043221A1 |
This photosensitive surface treatment agent contains a compound represented by formula (M1). (In formula (M1), R1 represents a hydrogen atom, a tert-butoxycarbonyl group, or an ester-based protecting group, R2 represents a hydrogen atom ...
|
|
WO/2024/040880A1 |
The present application provides a composite silicon carbide substrate and a preparation method therefor. The composite silicon carbide substrate comprises a single crystal layer, a bonding layer and a supporting layer stacked in sequenc...
|
|
WO/2024/041831A1 |
Disclosed are methods, systems, and computer software for predicting after-etch profiles of features at varying depths. A method can include accessing after-development resist profiles of features. The method can also include applying an...
|
|
WO/2024/040712A1 |
The present disclosure relates to the technical field of semiconductors, and provides a manufacturing method for a semiconductor structure, and a semiconductor structure. The manufacturing method for the semiconductor structure comprises...
|
|
WO/2024/042836A1 |
The present invention is a nitride semiconductor substrate comprising: a silicon substrate having a resistivity of 1000 Ω•cm or more or a base substrate equipped on the surface thereof with a silicon layer having a resistivity of 1000...
|
|
WO/2024/041867A1 |
A semiconductor device includes a first vertical field-effect transistor comprising a first set of vertical fins and a second set of vertical fins separated by a first isolation pillar structure. The semiconductor device further includes...
|
|
WO/2024/042698A1 |
In this semiconductor integrated circuit device, a first wiring layer includes a plurality of electrode pads (P) that are arranged side by side in a first direction and are connected to a first power supply, and a first wire extending in...
|
|
WO/2024/040448A1 |
A circuit board, comprising: a base substrate, an active pattern layer, and an electrical pattern layer, wherein the active pattern layer is arranged on one side of the base substrate and comprises a plurality of active patterns; and the...
|
|
WO/2024/040701A1 |
The present disclosure relates to the technical field of semiconductors. Provided is a patterning method, which is used for ameliorating the problem of an odd-even effect in a multi-patterning process. The patterning method comprises: pr...
|
|
WO/2024/041390A1 |
Provided are an electronic assembly package member (1) and a manufacturing method therefor. The electronic assembly package member (1) comprises: a first metal layer, a high-voltage transistor semiconductor die (10), a first molding comp...
|
|
WO/2024/042833A1 |
This substrate treatment method comprises: a step (S1) for immersing a substrate (W) in an alkaline treatment liquid (L); and a step (S2) for etching, by means of the treatment liquid (L), a polysilicon layer (Wc) filling a columnar rece...
|
|
WO/2024/042777A1 |
Provided is a group-III element nitride substrate that is capable of having an improved yield. A method for inspecting a group-III element nitride substrate according to an embodiment of the present invention comprises: preparing a group...
|
|
WO/2024/044274A1 |
A method includes receiving, by a processing device, first data generated by a first sensor of a substrate processing system. The first data is generated responsive to the first sensor receiving electromagnetic radiation from a substrate...
|
|
WO/2024/040587A1 |
A display substrate and a preparation method therefor, and a display apparatus. The display substrate comprises a base substrate (101), a pixel driving circuit layer (102) and an antenna layer (103), wherein the pixel driving circuit lay...
|
|
WO/2024/040515A1 |
A method for manufacturing a nitride-based semiconductor device is provided. The method includes steps as follows. An epitaxy structure is formed on a silicon-based substrate. An oxide structure is formed on the epitaxy structure. A mask...
|
|
WO/2024/040565A1 |
A packaging substrate and a manufacturing method therefor, and a functional substrate and a manufacturing method therefor. The manufacturing method for the packaging substrate comprises: providing an initial substrate (100), the initial ...
|
|
WO/2024/043138A1 |
A plasma processing device according to the present disclosure comprises a chamber, an introduction portion, a choke, a first conductor portion, and a second conductor portion. The introduction portion is configured to introduce electrom...
|
|
WO/2024/041049A1 |
A semiconductor structure is provided in which a phase change memory (PCM) device region including a PCM is located in a back side of a wafer. A PCM device back side source/drain contact structure connects the PCM to a first source/drain...
|
|
WO/2024/043065A1 |
A control unit of this plasma treatment device is configured to execute: (a1) a step for acquiring a first parameter at an input end and/or an output end of a first matching device; (a2) a step for acquiring a second parameter at an inpu...
|
|
WO/2024/041858A1 |
An approach forming semiconductor structure composed of a first plurality of vertical transport field-effect transistors (11B) in a lower semiconductor layer and a second plurality of vertical transport field-effect transistors (11A) in ...
|
|
WO/2024/042720A1 |
An adhesive film for circuit connection comprising a first adhesive layer having thermosettability, conductive particles partially embedded in one side of the first adhesive layer, and a second adhesive layer that has thermosettability a...
|
|
WO/2024/044022A1 |
A method includes providing a first substrate having a first surface and a second substrate having a second surface, where the first surface and the second surface each include a silicon-based dielectric layer, applying hydrogen plasma t...
|
|
WO/2024/040883A1 |
The embodiments of the present disclosure relate to the field of semiconductors. Provided are a semiconductor structure and a manufacturing method therefor. The structure comprises: a substrate, which comprises a first active area and a ...
|
|
WO/2024/041095A1 |
The present application relates to the technical field of package substrate manufacturing, and in particular to a package substrate having a micro-structured chamber and a manufacturing method therefor. The manufacturing method for the p...
|
|
WO/2024/043082A1 |
The present invention provides a technology for etching regions that have different opening sizes. The present invention provides an etching method that is carried out in a plasma processing apparatus that has a chamber. This etching met...
|
|
WO/2024/043070A1 |
This plasma treatment device comprises: a chamber; a substrate support part including an RF electrode; a first RF power supply that is joined to the chamber and that generates a first pulsed RF signal; a second RF power supply that is jo...
|
|
WO/2024/044462A1 |
Embodiments include semiconductor processing methods to form low-κ films on semiconductor substrates are described. The processing methods may include flowing one or more deposition precursors to a semiconductor processing system, where...
|
|
WO/2024/042621A1 |
The present invention provides technology that makes it possible to improve uniformity of substrate processing. The present invention comprises: a processing chamber that is for processing a substrate; a processing gas supply unit that...
|
|
WO/2024/043105A1 |
In the present invention, a transformer chip includes: an insulating body that is provided on a substrate; an isolation transformer; a first connection electrode and a second connection electrode; a first capacitor; a second capacitor; a...
|
|
WO/2024/044215A1 |
A computer readable medium includes instructions that, when executed by a processing device, cause the processing device to perform operations. Operations include processing a first substrate in a process chamber while the first substrat...
|
|
WO/2024/041122A1 |
Provided in the present disclosure are a high-electron-mobility transistor and a preparation method therefor. The high-electron-mobility transistor comprises a substrate, an epitaxial layer, a source electrode, a drain electrode, a gate ...
|
|
WO/2024/043675A1 |
The present invention relates to: a method for manufacturing a group III nitride semiconductor template, by which a high-quality group III nitride semiconductor layer can be formed on the top of a high heat dissipation support substrate ...
|
|
WO/2024/041186A1 |
The present application relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method therefor, and an electronic device, for use in mitigating the problem that different fins have di...
|
|
WO/2024/042784A1 |
The present invention provides a production method and a production apparatus, each of which is capable of producing a plurality of semiconductor components from one lead frame. The semiconductor components each have: a resin portion 2...
|
|
WO/2024/040698A1 |
Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method comprises: providing ...
|
|
WO/2024/042419A1 |
Provided is a storage device which can be micro-fabricated or highly integrated. This storage device comprises a memory cell and a first insulator. The memory cell comprises a capacitive element and a transistor disposed on the capacitiv...
|
|
WO/2024/042219A1 |
A composition of matter comprising a doped substrate a mask layer having a thickness of 2 nm or less on top of said substrate wherein a plurality of openings are present through said mask layer; and wherein a plurality of nanowires or na...
|
|
WO/2024/044216A1 |
A method for etching features in a stack is provided. A non-uniform metal or metalloid containing mask is formed over the stack. The stack is etched through the non-uniform metal or metalloid containing mask, wherein the etching sputters...
|
|
WO/2024/043584A1 |
A semiconductor wafer inspection device according to the present invention comprises: a chamber bowl having an open top, and having an accommodation space in which a semiconductor wafer is accommodated; a wafer chuck which is arranged in...
|
|
WO/2024/041164A1 |
The present invention proposes a liquid supply device and a substrate cleaning method. The liquid supply device comprises a nozzle, wherein a liquid inlet of the nozzle may use a tangential liquid intake method to promote gas-liquid sepa...
|
|
WO/2024/044146A1 |
Parameters from an inspection image representing mechanical vibrations and electromagnetic interference can be determined. An X-direction vibration spectrum can be determined based on the X-direction offsets. A Y-direction vibration spec...
|
|
WO/2024/042597A1 |
The purpose of the present invention is to provide semiconductor device manufacturing method and a semiconductor manufacturing device that, without requiring a complex gas supply system, can ensure processing efficiency and suppress cont...
|
|
WO/2024/043049A1 |
This film deposition method is a method for depositing a film of a crystalline oxide by a mist CVD method, in which a mist is fed together with a carrier gas to a heated substrate inside a film deposition zone surrounded by partitions. T...
|
|
WO/2024/043213A1 |
The present invention provides a composition which is capable of uniformly forming a thin film that contains a water-soluble cellulose by means of a spin coating method. A composition for forming a thin film according to the present di...
|
|
WO/2024/041626A1 |
Disclosed in the present application are a gate structure, a semiconductor device, and a method for preparing a semiconductor device. The gate structure comprises a gate portion and a field plate portion, wherein the field plate portion ...
|
|
WO/2024/043139A1 |
An etching method according to one exemplary embodiment of the present invention comprises: (a) a step for providing a substrate which is provided with a first film that has a recessed part and a second film that is arranged on the first...
|
|
WO/2024/042752A1 |
This warp correction system comprises a warp correction device and a relay unit. The warp correction device corrects warp in a first molded substrate and produces a second molded substrate. The relay unit is disposed between the warp cor...
|
|
WO/2024/041339A1 |
Disclosed are a semiconductor structure, and a scribe line structure and a method for forming same. The method for forming a scribe line structure comprises: forming a stack layer on a substrate, and defining a plurality of areas to be t...
|
|
WO/2024/043166A1 |
The present invention provides a technique which inhibits etching rate from decreasing. Provided is a device for treatment with a plasma including: a chamber; a substrate-supporting part disposed inside the chamber; a gas feed port which...
|
|
WO/2024/042829A1 |
Provided is a cylindrical grinding device that produces a slicing single crystal by performing cylindrical grinding in which the outer peripheral surface of a grinding single crystal is ground while the grinding single crystal is caused ...
|
