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WO/2024/051238A1 |
The present invention relates to a chip packaging structure and a preparation method. The chip packaging structure comprises a substrate, a chip, a thermal interface material layer, and a heat dissipation component. The chip is located o...
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WO/2024/053136A1 |
This plasma generation device comprises: an outer conductor (29) that is a conductive waveguide having an opening (34) on one end side; a first dielectric body (31) that extends along the principal axis of the outer conductor (29) within...
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WO/2024/052787A1 |
Provided is a semiconductor device having a novel configuration. This semiconductor device has: a first element layer on which a readout circuit is provided; a second element layer on which an amplification circuit is provided; and a thi...
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WO/2024/051920A1 |
The invention relates to a container (1) for vaporizing a precursor material and delivering the vaporized precursor material, comprising: - a receiving part (12) bounding an inner volume; - a number of subcarrier trays (4) arranged on to...
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WO/2024/051423A1 |
A chip (300) and a packaging method for a die (11). The die (11) comprises a photosensitive functional region (111). The packaging method comprises: forming, on the die (11), a support structure (12) surrounding the photosensitive functi...
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WO/2024/054763A1 |
In an example, a semiconductor device (10) includes an active trench region (22A) and an intersecting trench region (22C, 22CA, 22CB). The active trench region (22A) includes an active shield electrode (21A) and the intersecting trench r...
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WO/2024/053146A1 |
A semiconductor device manufacturing device (10) comprises a wafer holding device (12) that holds one or more chips (100) adhesively held on a surface of a dicing tape (120) along with the dicing tape (120), a pickup head (14) that picks...
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WO/2024/053523A1 |
In this semiconductor device manufacturing method, first a structure 200 is prepared, said structure 200 having an interposer 60, in which a plurality of groove sections 61 for dividing a front surface into a plurality of placement regio...
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WO/2024/053421A1 |
This abnormality management method for a conveying arm includes: an acquisition step for acquiring target data, which are transition data of an abnormality scale calculated on the basis of a feature quantity relating to a conveying opera...
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WO/2024/047137A1 |
A method comprising: providing an electrically-insulative wafer comprising a first surface, and a second surface for processing; and providing a layer on the first surface. The layer is non-metallic, electrically-conductive, and for elec...
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WO/2024/046632A1 |
The present invention relates to a method for connecting a cooler module (4) to a metal plate by means of a sintering method, wherein the cooler module (4) comprises a metallic housing (5) having a coolant inlet (7), a coolant outlet (8)...
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WO/2024/047820A1 |
In an output circuit (11) included in IO cells (10), an M1 wiring line (32a) has been disposed between transistor arrays (24a, 24b) included in output transistors (P1), the M1 wiring line (32a) being connected to the gates of the transis...
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WO/2024/049609A1 |
A method for forming a semiconductor device is disclosed. The method includes forming a first metal layer on top of an amorphous mask layer disposed over a substrate. The method includes forming a second metal layer that extends along ve...
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WO/2024/045343A1 |
The present invention relates to a semiconductor device and a manufacturing method therefor. The semiconductor device comprises at least two through-silicon via (TSV) electrical connection structures which are vertically stacked and elec...
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WO/2024/047784A1 |
A first semiconductor layer (102) is formed on a substrate (101) by crystal growth of a first nitride semiconductor in the direction of the c-axis. A second semiconductor layer (103) made of a second nitride semiconductor having a band g...
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WO/2024/047713A1 |
The present invention forms a film on a substrate by performing a cycle which includes the following steps a prescribed number of times: (a) a step for forming a first layer on a substrate by supplying a first starting material and an ad...
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WO/2024/046345A1 |
Provided in the present invention are a chuck structure of a semiconductor cleaning device, and a semiconductor cleaning device. The chuck structure comprises a chuck base body configured to bear a wafer, and a plurality of avoidance rec...
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WO/2024/046713A1 |
A semiconductor structure is presented including a first source/drain (S/D) epi region having a first contact completely wrapping around the first S/D epi region, the first contact electrically connected to a backside power delivery netw...
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WO/2024/048804A1 |
A foreign matter removal device comprises a chamber including a fluid, and a magnet assembly below the chamber. The chamber comprises a loading portion for loading a first object, a second object, and a third object into the fluid, a fir...
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WO/2024/046577A1 |
The invention relates to a method and a device for influencing a bonding wave (6) during the bonding of a first substrate (4) to a second substrate (4'), - wherein at least the first substrate (4) is fixed to a first substrate holder (1)...
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WO/2024/048004A1 |
This laminated structure comprises: an amorphous substrate that has an insulating surface; an alignment layer that has a pattern on the amorphous substrate; and a semiconductor layer that includes gallium nitride, the semiconductor layer...
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WO/2024/046241A1 |
The present application provides an epitaxial structure and a preparation method therefor. The preparation method for an epitaxial structure comprises: forming a buffer layer, a mask layer, and an epitaxial layer located in first through...
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WO/2024/045637A1 |
A display panel and a preparation method therefor. The preparation method comprises: providing a first substrate (300), one side of the first substrate (300) being provided with a plurality of Micro-LED chips spaced apart; providing a se...
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WO/2024/045757A1 |
Provided in the present invention are a 2.5D packaging structure and a preparation method. Packages each comprising an adapter plate, a chip and a packaging layer, which are electrically connected, are first prepared, the independently a...
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WO/2024/047783A1 |
A high electron mobility transistor according to an embodiment of the present disclosure comprises a heterojunction structure that includes a GaN channel layer in which two recesses are formed with a predetermined gap therebetween. The h...
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WO/2024/047999A1 |
A film formation device according to the present invention is characterized by comprising: an electrostatic chuck 31 that absorbs the surface of a substrate S opposite the film formation-side surface thereof; a first support member 41 th...
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WO/2024/048856A1 |
The present invention relates to a collection device using a fluid vortex to increase collection efficiency and, more specifically, to a collection device that maximizes the collection efficiency for a specific material to be collected, ...
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WO/2024/049022A1 |
A dry etching method according to the present invention is a method for performing dry etching of an object by using a plurality of reactive gases including a first reactive gas having a first diffusion rate and a second reactive gas hav...
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WO/2024/045426A1 |
Provided in the embodiments of the present disclosure are a light-emitting panel, an electronic device and a manufacturing method for a light-emitting panel. The manufacturing method comprises: providing a magnetic substrate; electrifyin...
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WO/2024/048227A1 |
This semiconductor device provided with a plurality of pixels which each emit light comprises: a first semiconductor substrate including transistors for pixel circuits that control light emission from the respective pixels; an obverse su...
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WO/2024/045467A1 |
The present disclosure relates to the field of semiconductors, and provides a method for manufacturing a semiconductor structure and a semiconductor structure. The method for manufacturing a semiconductor structure comprises: forming a f...
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WO/2024/047858A1 |
An upper base material 20 of this wafer placement table 10 comprises a ceramic base material 21 that has an electrode 22 built therein, and has a wafer placement surface 21a on the upper surface of the ceramic base material 21. A lower b...
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WO/2024/048767A1 |
[Problem] To provide a crystal having excellent crystallinity and a laminate structure, and an element, an electronic device, an electronic apparatus, and a system using same. [Solution] Provided is a laminate structure in which an epita...
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WO/2024/048156A1 |
The present invention provides: a resin composition which is curable at a relatively low temperature and which has a long pot life; a cured product; and a semiconductor device and an electronic component which include the cured product.ã...
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WO/2024/046578A1 |
The invention relates to a vacuum substrate holder (1) for fixing a substrate (13), comprising a) a first vacuum zone (5, 5', 5", 5"') with at least one first fixing element (4, 4', 4", 4"'), b) a second vacuum zone (5, 5', 5", 5"') with...
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WO/2024/045389A1 |
A wafer etching method, comprising the following steps: S1, mounting a plasma flow control device between a wafer (302) and a gas inlet (202a) of a plasma reaction chamber (200) of a plasma etcher; S2, placing the wafer (302) on a wafer ...
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WO/2024/049890A1 |
A retaining ring for a carrier head of a chemical mechanical polishing system includes an annular outer portion having an annular outer surface and a plurality of flanges projecting radially inward from the annular outer portion. Adjacen...
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WO/2024/049701A1 |
Methods for DRAM device with a buried word line are described. The method includes forming a metal nitride layer comprising lanthanum nitride (LaN) and a molybdenum conductor layer in a feature on a substrate. The method includes deposit...
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WO/2024/048157A1 |
A silicon carbide substrate according to the present invention has a main surface. The main surface is composed of an outer peripheral part which is a portion within 5 mm from the outer peripheral edge of the main surface, and a central ...
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WO/2024/045861A1 |
Embodiments of the present application provide a chip and a manufacturing method therefor, and an electronic device. The problem that a gate control capability of a chip decreases along with miniaturization of a device size is solved. Th...
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WO/2024/045268A1 |
The present disclosure relates to the technical field of semiconductors. Provided are a manufacturing method for a semiconductor structure, and a semiconductor structure. The manufacturing method for a semiconductor structure comprises: ...
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WO/2024/050175A1 |
A cooler for power electronics comprises: first mounting surfaces for first power electronics modules, respectively; second mounting surfaces for second power electronics modules, respectively, each of the first mounting surfaces being p...
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WO/2024/045864A1 |
Provided in the present application are a semiconductor device, a preparation method and an electronic device. The method comprises: forming, on a substrate, a plurality of stacked structures, which are arranged spaced apart from each ot...
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WO/2024/047305A1 |
The invention relates to a method for polishing the front face of a polycrystalline silicon carbide slab comprising a surface region at least partially work-hardened under the effect of grinding, comprising: - relative movement of a rota...
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WO/2024/045266A1 |
The embodiments of the present disclosure relate to the field of semiconductors. Provided are a manufacturing method for a semiconductor structure, and a semiconductor structure. The manufacturing method for a semiconductor structure com...
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WO/2024/046240A1 |
An epitaxial structure and a preparation method therefor. The preparation method for the epitaxial structure comprises: providing a substrate (11); forming a buffer layer (12) located on one side of the substrate (11); and forming an epi...
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WO/2024/048187A1 |
This semiconductor device comprises a semiconductor element, a conductive member, a conductive joining layer, and a first positioning member. The semiconductor element has a first primary surface electrode. The conductive joining layer c...
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WO/2024/048393A1 |
This multilayer structure comprises an amorphous substrate that has an insulating surface, an alignment layer that is arranged on the amorphous substrate, and a semiconductor pattern that contains gallium nitride and is arranged on the a...
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WO/2024/048005A1 |
This layered structure comprises: an amorphous substrate that has an insulating surface; an orientation layer that has a pattern on the amorphous substrate having the insulating surface; a semiconductor layer that contains a gallium nitr...
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WO/2024/048382A1 |
The present invention addresses the problem of providing a method for processing an object to be processed, said method exhibiting an excellent etching amount with respect to a metal layer including at least one metal selected from the g...
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