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WO/2024/053396A1 |
Provided is a sensor device that measures an external electric field with high measurement sensitivity. This sensor device is capable of measuring the electric field intensity of an external electric field. The sensor device comprises:...
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WO/2024/051405A1 |
A spray assembly, a semiconductor device, and a wafer processing method. An annular spray plate is provided, multiple independent spray regions are formed in an annular region of the spray plate, and the flow rate, concentration and the ...
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WO/2024/054803A1 |
Bonded structures and methods of forming a bonded structure are disclosed. A bonded structure can include a first element and a second element. The first element includes a first non-conductive field region and a first conductive feature...
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WO/2024/051228A1 |
The present application discloses a power device and a power apparatus. The power device comprises: a housing; a lead frame, comprising a base island area and a pin area, the housing and the base island area defining a chip accommodating...
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WO/2024/050909A1 |
Embodiments of the present disclosure provide a semiconductor device and a forming method therefor. The semiconductor device comprises: a substrate; and a plurality of storage arrays sequentially stacked on the substrate along a third di...
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WO/2024/053192A1 |
The present invention is characterized by comprising: an electrostatic chuck 31 which grabs, by suction, a surface on the opposite side to a film forming-side surface of a substrate S; a substrate support member 41 which supports a perip...
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WO/2024/055029A2 |
A system or method to fabricate a nano surface on a conductive device, including a high voltage DC power source, a pulse generator connected to the power source, a fluid container, in which the electrolyte solution is placed and a cathod...
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WO/2024/051335A1 |
The present invention relates to a liquid tension control method capable of improving wafer drying efficiency. The method comprises: Step 1, putting a wafer cassette connected to a swinging mechanism in a drying tank body, loading wafers...
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WO/2024/051888A1 |
The invention relates to a wafer holder for extensively electrically contacting a semiconductor wafer (40) comprising a metal body (10) with a metal flat side (12) offset by the offset height L on the upper side and a gas coupling (16) a...
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WO/2024/052551A1 |
The invention regards a method for nanofabricating a SiC-on-insulator material stack, comprising the steps of providing a SiC layer comprising a first proximal surface and a first distal surface, providing a Si substrate comprising a SiO...
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WO/2024/052695A1 |
A method of separating a semiconductor device from a substrate comprises the steps of: providing a semiconductor structure comprising a semiconductor device, a substrate, and a porous layer of semiconductor material between the semicondu...
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WO/2024/053521A1 |
This semiconductor device production method is for preparing a structure 200 including: an interposer 60 divided into a plurality of installation areas 65 by groove sections 61 formed therein; and semiconductor elements 202a, 202b arrang...
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WO/2024/053022A1 |
A semiconductor device comprises a gate trench (22) formed in an active region (50); a gate insulating film (10) and a gate electrode layer (11) formed inside the gate trench (22); a gate wiring electrode (15) formed on an interlayer ins...
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WO/2024/052149A1 |
A method of growing a layer of ß-Ga2O3 on a substrate comprising the following steps: Polishing the substrate to a roughness of not more than 300 x 10-12 m measured by AFM, etching the substrate using an aqueous solution of phosphoric a...
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WO/2024/054802A1 |
When a high intensity Second Harmonic Signal (SHG) probing laser is incident on a wafer surface under test, the SHG response is generally the combination of a few components: contributions from interfaces between material types (e.g., th...
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WO/2024/050907A1 |
Disclosed in embodiments of the present disclosure are a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method comprises: providing a substrate; forming a laminated s...
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WO/2024/051282A1 |
Embodiments of the present application provide an IGBT device manufacturing method and an IGBT device. The manufacturing method comprises: forming an epitaxial layer of a second doping type on a substrate; trenching the upper surface of ...
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WO/2024/054413A1 |
An amorphous silicon layer or amorphous boron layer can be deposited on a substrate using one or more silicon or boron-containing precursors, respectively. Radical species are provided from a plasma source or from a controlled reaction c...
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WO/2024/054463A1 |
Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. The methods include treating a surface of a metal gate stack with a radical treatment. The radical treatment may be used to treat one...
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WO/2024/053442A1 |
Provided is a plasma processing device comprising: a processing vessel that has a stage on which a substrate is placed; a first electrode to which a high-frequency power for plasma generation is supplied; a second electrode that faces th...
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WO/2024/054369A1 |
A method of forming a semiconductor memory device includes simultaneously filling a top portion of a first high aspect ratio (HAR) structure and a top portion a second HAR structure with a silicon-containing sacrificial layer by a cycle ...
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WO/2024/050866A1 |
A gallium oxide device preparation method based on high-temperature annealing technology, and a gallium oxide device. The method comprises: preparing a barrier layer on the surface of a gallium oxide wafer, the barrier layer having a fun...
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WO/2024/052773A1 |
The present invention provides a transistor which enables the achievement of miniaturization. The present invention also provides a transistor which has good electrical characteristics. This semiconductor device comprises first to third ...
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WO/2024/052968A1 |
The present invention discloses a method for producing a semiconductor device. This method for producing a semiconductor device comprises: a step for preparing a structure that comprises an interposer which has a first main surface and a...
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WO/2024/054710A1 |
A chip includes a first active region, first gates extending over the first active region in a first direction, wherein the first gates correspond to a first transistor, and second gates extending over the first active region in the firs...
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WO/2024/019774A9 |
Exemplary methods of fabricating high quality quantum computing components are described. The methods include removing native oxide from a deposition surface of a silicon substrate in a cleaning chamber of a processing system, and transf...
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WO/2024/053395A1 |
Provided is a technique for reducing electrical resistance and suppressing generation of particles in a component to be used for a plasma processing device. The component to be used for the plasma processing device comprises: a conduct...
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WO/2024/052952A1 |
A semiconductor device according to the present disclosure comprises: a drift layer including a first pillar region of a first conduction type alternating with a second pillar region of a second conduction type; a base region of the seco...
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WO/2024/053569A1 |
The present invention relates to a GaN crystal which comprises a Zn-doped GaN layer, wherein: the Zn-doped GaN layer has a Zn concentration of 1.0 × 1016 atoms/cm3 to 1.0 × 1020 atoms/cm3; and the full width at half maximum of a rockin...
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WO/2024/053414A1 |
Provided is a property prediction system (100) comprising: a prediction computer (10); a measurement computer (20); and a measurement instrument (30). The measurement computer (20) is provided with a processor (21) that acquires the elec...
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WO/2024/053115A1 |
This simulation method comprises: preparing a simulation model of a semiconductor device including a substrate, an element, a connecting part which electrically connects the substrate and the element, and a reinforcing material which is ...
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WO/2024/050910A1 |
Embodiments of the present disclosure relate to the technical field of semiconductors, and provide a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate; a lower electrode layer...
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WO/2024/051066A1 |
Provided in the present invention are a semiconductor substrate structure and a device. The semiconductor substrate structure comprises a substrate, conductive pillars, transverse insulation layers and vertical insulation layers. Vertica...
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WO/2024/051334A1 |
An isopropanol and nitrogen mixing tank applied to wafer drying devices. The interior of a mixing tank (207) is of a three-layer structure comprising a vortex mixing channel (216), a buffer backflow tank (217) and a hot water bath area (...
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WO/2024/052617A1 |
The invention relates to a method for manufacturing a transfer structure (100) comprising the following steps: i) providing an intermediate substrate (110); ii) bonding chips (121, 122) to a first surface of an intermediate substrate (11...
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WO/2024/051333A1 |
Disclosed is an integrated wafer drying system, comprising: a wafer swinging module which is externally hung on one side of a process tank and is used for performing a swinging motion on a wafer in the drying process; a pipeline conveyin...
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WO/2024/054856A1 |
Methods are disclosed for improving one or more of jitter/timing, signal-to-noise ratio, signal integrity, stability, and repeatability of generation and measurement of Second Harmonic Generation (SHG) signals generated by a sample upon ...
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WO/2024/053384A1 |
The present invention is a method for producing a base substrate for a single crystal diamond multilayer substrate, the method comprising a step for preparing an initial substrate and a step for forming an intermediate layer comprising a...
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WO/2024/054351A1 |
A reflector plate assembly for processing a substrate includes a reflector plate having a first surface, wherein the first surface is a bare polished surface, a reflector disk embedded within the reflector plate from the first surface, a...
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WO/2024/051144A1 |
The present invention relates to a preparation method for a small-sized high-density copper pillar. The preparation method comprises: providing a substrate, and etching the substrate to form required copper pillar trenches in the substra...
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WO/2024/054353A1 |
A direct patterning deposition mask for OLED deposition is provided where the mask includes a sapphire substrate; and a Silicon Nitride (SiN) membrane. The sapphire substrate thickness may be between 0.7 and 2 mm. The sapphire substrate ...
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WO/2024/053900A1 |
A door baffle arranged to open and close at least one end of a process tube comprising: a baffle part formed to block one end part of the process tube; and an assembly part which is connected to the perimeter of the baffle part and is fo...
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WO/2024/052774A1 |
The present invention provides a semiconductor device which enables the achievement of miniaturization or high integration. According to the present invention, a second layer, a mask and a first resist mask are sequentially formed on a f...
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WO/2024/053623A1 |
Provided as one embodiment is an etchant composition having excellent storage stability. An embodiment of the present disclosure relates to an etchant composition for etching layers containing at least one metal, the etchant compositio...
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WO/2024/052783A1 |
A semiconductor device includes a doped gallium arsenide (GaAs) substrate, and buffer columns grown or deposited on the doped GaAs substrate. Each of the buffer columns includes NIPI (n-type/intrinsic/p-type/intrinsic) or NIPIN (n- type/...
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WO/2024/053390A1 |
The present invention provides: a polishing agent which is capable of polishing a surface to be polished, the surface containing a resin, highly flat at a high rate; an additive solution for polishing agents; and a polishing method. Th...
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WO/2024/053837A1 |
An electronic device according to an embodiment may comprise: a substrate; a first integrated circuit connected to the substrate; a second integrated circuit connected to the substrate via the first integrated circuit and arranged over o...
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WO/2024/052615A1 |
The invention relates to a method for treating a polycrystalline silicon carbide wafer, which method comprises: characterising (R2) a surface condition of a front face of the polycrystalline silicon carbide wafer; when the characterised ...
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WO/2024/051232A1 |
A method for manufacturing a semiconductor structure, and a semiconductor structure. The method for manufacturing a semiconductor structure comprises: providing a substrate (5), and forming, on the substrate (5), at least two stacked str...
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WO/2024/051862A1 |
Provided is a procedure control method for a semiconductor process based on machine learning, which relates to the technical field of epitaxial semiconductor film growth. The method comprises the following steps: S1, acquiring current pr...
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