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JPH0492516A |
PURPOSE: To obtain the conversion outputs uniform in terms of time with a small hardware quantity by providing (n) pieces of latch circuits where a 1st latch fetches the bit corresponding to the data with each clock corresponding to the ...
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JPH0490622A |
PURPOSE: To perform bit order conversion at a high speed by performing the bit order conversion with hardware processing utilizing a data selector. CONSTITUTION: A shift register 15 converts input picture data Din-S to parallel data. An ...
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JPH0488422A |
PURPOSE: To shorten the maximum wiring length and to reduce the wiring area, to reduce the size of the constitution, and to make the operation speed fast by simplify the layout of connection wiring. CONSTITUTION: Selectors which constitu...
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JPH0482444A |
PURPOSE: To easily detect the error of a signal and to display it as an error flag by extracting a period which is assumed as the error as the pulse period of an error detection permission signal when the fluctuation of a data occurs. CO...
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JPH0479422A |
PURPOSE: To increase the operation speed by providing first and second data buffer circuits, selecting these circuits to read out stored parallel data and converting it to a serial data. CONSTITUTION: An address control buffer circuit 1 ...
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JPH0474020A |
PURPOSE: To realize low speed synchronization serial/parallel conversion with simple constitution without use of an elastic storage ES by writing and reading a parallel data being an output of a shift register to/from a latch in the S/P ...
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JPH0470013A |
PURPOSE: To omit the frame synchronizing circuits and the parallel signal rearraying circuits in number accordant with the array state of parallel signals and to extremely reduce the circuit scale by applying the feedback control to the ...
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JPH0461442A |
PURPOSE: To reduce the occupied area and power consumption of an integrated circuit by selecting either of two bit units (2 bits and 8 bits) and using the selected unit for the bit unit of multiplex/demultiplex processing. CONSTITUTION: ...
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JPH0461441A |
PURPOSE: To reduce the occupied area and power consumption of an integrated circuit by using one gate array so as to execute multiplex processing of a parallel signal and demultiplex processing of serial data bus information into a paral...
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JPH0456927A |
PURPOSE:To increase the transfer speed and to reduce noises by employing optical transmission instead of electric transmission. CONSTITUTION:According to the reference signal supplied from a synchronizing signal generator 4, voltage appl...
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JPH048980B2 |
PURPOSE:To solve a call disabled state and to continue serial transfer, by switching to the 2nd transmission line through a switching means when the 1st transmission line is in the call disabled state. CONSTITUTION:A transmission and rec...
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JPH0444699A |
PURPOSE: To enable a high-speed operation by parallelly outputting data to be serially inputted for every N number of data. CONSTITUTION: The data is read out by reading it out from data output lines 161-16N and after completely reading ...
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JPH0444698A |
PURPOSE: To unnecessitate an external clock circuit by providing a circuit to turn a state memory in a final step to a no-data state when the data stored in the data memory in the final step is read out by an external control signal. CON...
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JPH0438017A |
PURPOSE: To expand a timing margin and to quicken an operation by writing a synchronous signal and shifting it by a shift register, outputting a clock pulse shifted by one period each so as to allow a flip-flop to latch sequentially an i...
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JPH0435226A |
PURPOSE: To decrease mis-detection of a communication control pattern in a general communication data by applying changeover control only when a reception data is a communication control pattern in which detection patterns are consecutiv...
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JPH0435225A |
PURPOSE: To prevent malfunction due to a transmission delay or a waveform distortion by devising the circuit such that a data latch circuit latches a parallel video data in N(≥16) bits and an N:M data selector circuit outputs an N bit ...
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JPH0433416A |
PURPOSE: To prevent the deterioration in the transmission efficiency by sending a parallel signal bit by bit sequentially and serially to an external transmission line according to a timing signal sent with the input of a parallel signal...
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JPH0413279A |
PURPOSE:To surely extract a synchronizing signal even when a little bit error occurs by using the characteristics of the input signal scramble processing of a CD-ROM. CONSTITUTION:The synchronizing signal is extracted by converting an in...
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JPH03292698A |
PURPOSE: To miniaturize the circuit constitution and to eliminate the change for each clock of the parallel output by constituting each register of three latches. CONSTITUTION: Data inputted to a first latch 31 of a register 1 is sent to...
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JPH03274921A |
PURPOSE: To change a bit length without changing circuit configuration by outputting the plural kinds of PCM signals to be incremented by an address counter from a memory to one bit. CONSTITUTION: An address counter 1 counts a clock CK a...
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JPH03262333A |
PURPOSE: To attain high speed operation by extracting an output of n-set of flip-flops of a shift register as a parallel data in a timing given by a frequency division output from a frequency divider circuit. CONSTITUTION: An initial val...
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JPH0373182B2 |
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JPH03258120A |
PURPOSE: To warrant a conversion function even when a frame signal is changed by applying serial/parallel conversion in response to a timing signal from a gate circuit when each frequency division output of a counter circuit goes to all ...
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JPH0371818B2 |
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JPH0370415B2 |
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JPH03244217A |
PURPOSE: To simplify circuit configuration and to reduce energy consumption by always supplying a logic level 1 to the second data input terminal of a D-flip-flop(DFF) in the first step and supplying the output of the DFF in the final st...
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JPH0398535U |
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JPH03230622A |
PURPOSE: To save the area of a semiconductor device shared on a semiconductor integrated circuit by providing a small-sized 2nd decoding circuit group converting only an address and a data into parallel from a serial state to a single 1s...
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JPH03219736A |
PURPOSE: To make active and standby data coincident in a short time by comparing all combinations of n-string of parallel data obtained from active/standby n-bit memory circuits and discriminating the result of comparison. CONSTITUTION: ...
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JPH03216025A |
PURPOSE: To save circuits unable to be integrated considerably by providing a circuit diciding a phase difference between an input clock and a retiming clock at a prescribed threshold level and inverting the phase of the retiming clock a...
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JPH0358208B2 |
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JPH0357661B2 |
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JPH03184425A |
PURPOSE: To make it possible to process a data word at a high data rate by dividing a data word to be converted into sections shorter than the length of the data word and corresponding to the bit length of a shift register by the use of ...
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JPH0377577U |
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JPH03175743A |
PURPOSE: To make it completely unnecessary to use a clock signal for restoration processing by executing conversion processing by a converter provided with (n) signal detecting signals and restoring the converted signal into the original...
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JPH03503105A |
An information processing system includes a transmitter, which converts parallel information to serial, and a receiver, which receives the serial information and reconverts the same to parallel for use by a further processing unit. Struc...
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JPH0339424B2 |
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JPH03139020A |
PURPOSE: To satisfactorily operate the serial/parallel conversion of each word by converting an input bit sequence by a serial/parallel converter, providing a control circuit which indicates synchronizing offset from the word boundary of...
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JPH03135125A |
PURPOSE: To realize circuit arrangement constituted of processors operating in parallel by connecting a bi-directionally controllable interface and plural interfaces with an interface processor connected with input and output signals. CO...
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JPH03129926A |
PURPOSE: To correct an error of the value of a counter generated once to a correct value by resetting the contents of the counter by a clock (LRCK) for showing a sampling period, even if noise is superposed on a bit clock signal (BCLK) f...
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JPH03124126A |
PURPOSE: To form a signal extraction circuit with small circuit scale by using only one control signal to control a signal extraction means extracting a parallel data from a serial data and a signal latch means latching a parallel data r...
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JPH03121626A |
PURPOSE: To obtain a simple and small sized serial/parallel conversion circuit suitable for circuit integration and possible for high speed operation by changing a shift direction and an output signal extraction latch circuit for each fr...
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JPH03117220A |
PURPOSE: To prevent production of an invalid data by providing a storage means, a parallel/serial conversion means and a control means and applying parallel/serial conversion to the remaining data while skipping an invalid data when the ...
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JPH0346243U |
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JPH0344934U |
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JPH0389719A |
PURPOSE: To reduce the number of gates by using a gate circuit inputting plural data strings in parallel and outputting them at the timing of a timing pulse, and a shift register inputting the output and outputting data in a prescribed o...
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JPH0326583B2 |
PURPOSE:To keep synchronization between the transmission side and the receiving side at the transfer of continuous serial data and to protect the transfer data by providing a receiving clock stopping circuit and a low level detecting cir...
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JPH0382225A |
PURPOSE: To simplify the circuit constitution and to make the scale of the circuit constitution by implementing the insertion of an auxiliary code and the auxiliary code rule violation processing simultaneously. CONSTITUTION: The circuit...
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JPH0377431A |
PURPOSE: To reduce the number of circuit components, the chip size and the cost by providing a master latch circuit for fetching a signal data signal, and a data signal latch circuit for each channel. CONSTITUTION: A master latch circuit...
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JPH0371724A |
PURPOSE: To send a signal synchronized surely to an output highway by storing tentatively a parallel binary signal into a shift register synchronously with a clock signal being a reference again and outputting the binary signal to the ou...
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