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Matches 251 - 300 out of 857,375

Document Document Title
WO/2019/037457A1
Disclosed are a shift register, drive method thereof, drive control circuit, and display device. The shift register comprises: an input sub-circuit (1), a first control sub-circuit (2), a second control sub-circuit (3), a third control s...  
WO/2019/040138A1
A non-volatile storage apparatus is proposed that includes a plurality of serially connected non-volatile reversible resistance-switching memory cells, a plurality of word lines such that each of the memory cells is connected to a differ...  
WO/2019/040503A1
Self-referencing memory device, techniques, and methods are described herein. A self-referencing memory device may include a ferroelectric memory cell. The self- referencing memory device may be configured to determine a logic state stor...  
WO/2019/039200A1
Provided is a fluorinated ether compound, which can be used advantageously as a lubricant material for a magnetic recording medium, the lubricant material being capable of forming a lubricant layer having excellent chemical resistance an...  
WO/2019/038409A1
A superconducting logic element (1), comprising: a superconducting tunnel junction (10) comprising a first (20) and a second (30) superconductor; a first insulating ferromagnet (40) in contact with the first superconductor (20), configur...  
WO/2019/040951A1
A method for assisting a plurality of authors to generate a group video. The method comprises connecting a first electronic device of a first author with a server that provides communication among the plurality of authors; allowing the f...  
WO/2019/040871A1
The present invention solves the unmet need by providing a method for encoding and storing digital information in DNA or the sugar phosphate backbone of DNA or analogous structural mediums by use of expanded alphabet channels and derivat...  
WO/2019/039265A1
A fluorine-containing ether compound characterized by being represented by formula (1). R1–R2–CH2–R3–CH2–R4–R5 (1) (In formula (1), R3 indicates a perfluoropolyether chain. R2 and R4 indicate a divalent linking group having a...  
WO/2019/040403A1
The present disclosure includes apparatuses and methods related to sensing operations in memory. An example apparatus can perform sensing operations on an array of memory cells by applying a first signal to a first portion of the array o...  
WO/2019/040194A1
Numerous embodiments for an improved sense amplifier circuit for reading data in a flash memory cell are disclosed. The embodiments each compare current or voltage measurements from a data block with a reference block to determine the va...  
WO/2019/038618A1
A sense amplifier and a semiconductor device which are less likely to be influenced by a variation in transistor characteristics and their operation methods are provided. An amplifier circuit in a sense amplifier includes a first circuit...  
WO/2019/040811A1
A method for combining a plurality of video files with a tune and a recording medium storing an executable program for implementing the method. The method comprises transmitting a service request from an electronic device to a synchroniz...  
WO/2019/038649A1
An Apparatus and method for enhancing read performance in a two-dimensional magnetic recording (TDMR) system, including a grid defining a plurality of read elements, by timing recovery. The method can include the steps of filtering by a ...  
WO/2019/037020A1
Disclosed is a four-dimensional (4D: 3D+time) multi-plane broadband imaging system capable of recording 3D multi-plane multiple images in real time. The imaging system comprises: one or more non-reentry quadratically distorted (NRQD) gra...  
WO/2019/040256A1
Techniques for memory I/O tests using integrated test data paths are provided. In an example, a method for operating input/output data paths of a memory apparatus can include receiving, during a first mode, non-test information at a data...  
WO/2019/037706A1
The disclosure relates to technology for providing determined future fields of view (FoVs) of a 360 degree video stream in a network having multiple video streams corresponding to multiple FoVs. FoV interest messages including requests f...  
WO/2019/036593A1
In some examples of the disclosure, a parameter override mechanism may include a variable length configuration data table with entries for specific models of memory devices. The configuration data table entries may include override param...  
WO/2019/035391A1
The present disclosure includes a server apparatus, a recording method, a non-transitory computer-readable, and a system. In one example, the server apparatus includes a recording unit and a controller. The controller is configured to re...  
WO/2019/035390A1
The present disclosure includes an information processing apparatus, an information processing method, a non-transitory computer-readable medium, and a system. In one example, the information processing apparatus is a camera. The camera ...  
WO/2019/036071A1
A system includes multiple memory banks (12) that store data. The system also includes an address path (40) coupled to the memory banks (12) that provides a row address to the memory banks (12). The system further includes a command addr...  
WO/2019/033783A1
Provided are a shift register unit, a driving method, a gate driving circuit and a display apparatus. The shift register unit comprises: a pull-up node state maintaining circuit, connected to a pull-up node and an input end of a first co...  
WO/2019/036236A1
A script synchronization interface system is disclosed for synchronizing a script, shot properties, and one or more video files by mapping associated metadata. The script synchronization interface system includes an interactive script se...  
WO/2019/033823A1
A shift register unit, comprising a first output control circuit (10), a first output circuit (20), a second output control circuit (30), a second output circuit (40), a reset circuit (50), and a node setting circuit (60). The node setti...  
WO/2019/033441A1
Disclosed in the embodiments of the present invention are a sound volume adjustment method and apparatus, a mobile terminal, and a storage medium, the method comprising: when it is detected that a terminal device performs the playback of...  
WO/2019/036229A1
Apparatuses and methods for latching redundancy repair addresses at a memory are disclosed. An example apparatus includes block of memory including primary memory and a plurality of redundant memory units and repair logic. The repair log...  
WO/2019/036684A1
A method comprising the steps of responding to expiration of a timer, transmitting a signal from the timer to circuitry; responsive to receiving the signal, retrieving by the circuitry (i) first values stored in an analog array, and (ii)...  
WO/2019/034108A1
A method and device for storing video data applied to smart glasses. The method comprises: transmitting a pairing instruction to a mobile terminal; if the pairing between smart glasses and the mobile terminal is successful, receiving a v...  
WO/2019/036079A1
A memory device and associated techniques for reducing read disturb of memory cells during a sensing process. The drain-end select gate transistors of unselected sub-blocks are made temporarily conductive for a time period during the ram...  
WO/2019/033647A1
The present invention is applied in the technical field of electronic communications, and provides an error correction method, apparatus and device for a flash memory, and a computer readable storage medium. The error correction method c...  
WO/2019/036072A1
Devices, systems, and methods include controls for on-die termination (ODT) and data strobe signals. For example, a command to de-assert ODT for a data pin (DQ) during the read operation. An input, such as a mode register, receives an in...  
WO/2019/036257A1
The present disclosure relates generally to the field of power supply wiring in a semiconductor device. In one embodiment, a semiconductor device is disclosed that includes, an uppermost metal layer including a power supply enhancing wir...  
WO/2019/036360A1
Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured...  
WO/2019/033599A1
The present application discloses a shift-register circuit used as a shift-register unit of current stage including a control sub-circuit coupled to a shift-register unit of previous stage and configured to recharge a pull-up node of the...  
WO/2019/033009A1
Systems and methods are disclosed for preparing and evolving atomic defects in diamond. Silicon vacancy spins may be cooled to temperatures equal to or below 500 mK to reduce the influence of phonons. The cooling, manipulation, and obser...  
WO/2019/031068A1
This base unit is provided with: a base unit chassis that supports a spindle motor; a heat dissipating member that dissipates heat to a base unit chassis side, on which a disc is not mounted, said heat having been generated from a stator...  
WO/2019/032249A1
A method for programming a ReRAM cell including a ReRAM device connected in series with an access transistor includes biasing the ReRAM cell with a programming potential that configures the access transistor in a common-source configurat...  
WO/2019/032327A1
Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify vertical alignment between data transmitted using multi-level signaling. Such multi-leve...  
WO/2019/032293A1
A driver of a multi-level signaling interface is provided. The driver may be configured reduce noise in a multi-level signal (e.g., a pulse amplitude modulation signal) generated by the driver using switching components of different pola...  
WO/2019/032562A1
The present disclosure includes apparatuses comprising replaceable memory. An example apparatus may include a controller and a memory package coupled to the controller and including a plurality of memory dies. At least one of the memory ...  
WO/2019/029494A1
The present application provides a mobile terminal, a memory and a record file editing method, said editing method comprising: entering a recording mode according to a starting instruction of a user; detecting environment sound sources a...  
WO/2019/032151A1
As described above, certain modes of operation, such as the Fast Zero mode and the ECS mode, may facilitate sequential access to individual cells of a memory array. To facilitate this functionality, a command controller may be provided, ...  
WO/2019/032407A1
In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and t...  
WO/2019/032328A1
A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled...  
WO/2019/030971A1
Provided is a spacer which is used in a magnetic disk device, the spacer: prevents the occurrence of vibration of a magnetic disk that is alternately layered with the spacer; exhibits little thermal expansion; has high precision; and exh...  
WO/2019/032271A1
Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without in...  
WO/2019/030500A1
Broadly speaking, embodiments of the present technique provide a 3D interconnected die stack for transferring a data signal between die structures, the stack comprising on a first die structure a transmitter comprising a synchronising sp...  
WO/2019/032270A1
Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify peak-to-peak voltage differences between the amplitudes of data transmitted using multi-...  
WO/2019/032329A1
A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in ...  
WO/2019/032455A1
Data bit inversion tracking in cache memory to reduce data bits written for write operations is disclosed. In one aspect, a cache memory including a cache controller and a cache array is provided. The cache array includes one or more cac...  
WO/2019/031226A1
This spin current magnetoresistive effect element is provided with: a magnetoresistive effect element; a spin orbit torque wire which extends in a first direction intersecting a stacked direction of the magnetoresistive effect element, a...  

Matches 251 - 300 out of 857,375