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Patent Searching and Data


Matches 251 - 300 out of 854,772

Document Document Title
WO/2018/060656A1
The invention relates to a supercapacitor comprising: an electrolyte having a first end and a second end opposite the first end; a first electrode (E1) in contact with the first end of the electrolyte; and a second electrode (E2) in cont...  
WO/2018/063741A1
Cache memory clock generation circuits for reducing power consumption and read errors in cache memory are provided. In one aspect, a cache memory clock generation circuit employs detector circuit configured to receive a way address and g...  
WO/2018/062189A1
The present invention addresses the problem of providing: an Ni-Ta system alloy which is free from composition unevenness and has improved mechanical strength, and wherein Ta compound phases are finely dispersed by adding a predetermined...  
WO/2018/061267A1
The present invention is provided with: a front surface plate 34 fixed to a hard disc drive (HDD) 30; and a cover 20 attached to the front surface plate 34. A cover 20 can slide in the taking out direction between a first position close ...  
WO/2018/064285A1
Systems and methods are described for providing an image validation module. The image validation mobile enables capture, enhancement, validation, and upload of a digital image to a networked computing service, applying criteria that corr...  
WO/2018/063570A1
Technologies for a physically unclonable function with magnetic tunnel junctions (MTJs) is disclosed. An MTJ may have a fixed layer and a free layer. The MTJ may have two stable states: one in which the orientation of the magnetization o...  
WO/2018/063177A1
The present disclosure relates to the fabrication of spin transfer torque memory devices, wherein a spin transfer torque element is connected to a PMOS transistor. In one embodiment, the spin transfer torque element may have a fixed side...  
WO/2018/063730A1
Aspects of the embodiments are directed to systems, methods, and devices for generating a design of experiments (DOE) matrix, the DOE matrix comprising a set of possible combinations of values for a plurality of electrical parameters; it...  
WO/2018/063916A1
Aspects disclosed herein relate to techniques and an efficient architecture for enabling multi-way reads on highly associative content addressable memory (CAM) arrays. For example, a method for performing a tag search of a tag array can ...  
WO/2018/063735A1
Integrated circuits may include dual mode memory cells. Dual mode memory cells may be operated in a lookup-table mode or a memory mode. A dual mode memory cell may have configuration ports for supporting a configuration operation and use...  
WO/2018/063308A1
A two transistor, one resistor gain cell and a suitable storage element are described. In some embodiments the gain cell has a resistive memory element coupled to a common node at one end to store a value and to a source line at another ...  
WO/2018/063164A1
Embodiments include a resistive random access memory (RRAM) memory cell which is the same as a RRAM storage cell. The RRAM storage cell has a resistive material layer and a semiconductor layer between two electrodes, where the semiconduc...  
WO/2018/063728A1
Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of inde...  
WO/2018/059204A1
An audio device, comprising a housing (101), a circuit board (102), a rotating shell (104), a contact switch (105), and a trigger (106); the circuit board (102) is disposed in the housing (101); the housing (101) is rotatably connected t...  
WO/2018/059093A1
A shift register unit, a gate scanning unit, a drive method and a display device. The shift register unit comprises: a reset module (300), configured to transmit, under control of a reset control signal input end, a signal of a signal co...  
WO/2018/056105A1
The present technique relates to an information processing apparatus, an information processing method, a program and an information processing system with which a schedule for recording programs listed in a search result can be easily s...  
WO/2018/057766A1
A method and related apparatus for using an indication of RRAM cell resistance to determine a write condition are disclosed. A cell characteristic of an RRAM cell is determined to a finer resolution than a data read value. A write condit...  
WO/2018/057226A1
An integrated circuit (IC), as a computation block of a neuromorphic system, includes a time step controller to activate a time step update signal for performing a time-multiplexed selection of a group of neuromorphic states to update. T...  
WO/2018/057429A1
A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory...  
WO/2018/057228A1
Provided are a method and apparatus for programming non-volatile memory using a multi-cell storage cell group to provide error location information for retention errors. Each storage cell in the non-volatile memory is programmed with thr...  
WO/2018/057460A1
Metal-oxide semiconductor (MOS) transistor offset-cancelling (OC), zero-sensing (ZS) dead zone, current-latched sense amplifiers (SAs) (CLSAs) (OCZS-SAs) for sensing differential voltages are provided. An OCZS-SA is configured to amplify...  
WO/2018/057137A1
Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes an input pad, an input buffer including a first input node and a second input node, a switch that couples the first input...  
WO/2018/055614A1
A method for detecting errors is performed on a data string which includes an information portion and a redundancy portion. The information portion includes two or more sub-strings. The method includes generating respective redundancy wo...  
WO/2018/057191A1
The embodiments herein describe technologies of initializing resistive memory devices (e.g., non-volatile and volatile memory devices). In one method, a first voltage is applied across a resistance change material of a memory cell to for...  
WO/2018/057400A1
Approaches, techniques, and mechanisms are disclosed for manufacturing and operating high density memory systems. The high density memory systems can increase the amount of memory available to a computing system by allowing the connectio...  
WO/2018/057014A1
Disclosed herein are asymmetric selectors for memory cells, and related devices and techniques. In some embodiments, a memory cell may include: a storage element; and a selector device coupled to the storage element, wherein the selector...  
WO/2018/055455A1
The technology relates to processing one or more audio streams. The processing may include segmenting the one or more audio streams into structural components comprising a tonal stream and a transient stream. The tonal stream and the tra...  
WO/2018/054222A1
A multiple disk loader apparatus includes a plurality of rods. Each rod has a pair of pins extending radially from a side of the rod. The pair of pins are spaced circumferentially around the rod with respect to each other. Each pin has a...  
WO/2018/055768A1
The number of selectable chips is increased without adding signal lines to a general-purpose memory controller. A semiconductor storage device is provided with: a memory controller; a plurality of memory chips; a selection unit connected...  
WO/2018/055733A1
This storage device comprises a first memory cell and a second memory cell adjacent to the first memory cell, and a sequencer which, when reading data from the first memory cell, performs a first read operation on the second memory cell,...  
WO/2018/057717A1
Certain exemplary embodiments can provide a system, machine, device, manufacture, circuit, composition of matter, and/or user interface adapted for and/or resulting from, and/or a method and/or machine-readable medium comprising machine-...  
WO/2018/055171A1
A method of erasing data using a file-based protocol from a data storage apparatus for repurposing, reallocation to a new user or retirement of the data storage apparatus, the data storage apparatus comprising a memory using a file-based...  
WO/2018/057896A1
Provided are a neuromorphic computing device, memory device, system, and method to maintain a spike history for neurons in a spiking neural network. A neural network spike history is generated in a memory device having an array of rows a...  
WO/2018/051140A1
A method of combining data, the method comprising: receiving video data, the video data corresponding to recorded video having a video duration determined by a user; selecting backing audio data, the backing audio data corresponding to b...  
WO/2018/052688A1
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Before reading a memory cell, the voltage on an access line of the memory cell may be initialized to a value associated with the threshold vo...  
WO/2018/052667A1
Methods and apparatuses for generating probabilistic information for error correction using current integration are disclosed. An example method comprises sensing a first plurality of memory cells based on a first sense threshold, respon...  
WO/2018/052596A1
Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data...  
WO/2018/053413A1
In embodiments of the present disclosure improved capabilities are described for an asset intelligence platform for organizing information collected and stored on or with respect to large fleets of asset, such as used in connection with ...  
WO/2018/052697A1
A memory and apparatus are disclosed. The memory includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory ce...  
WO/2018/052561A1
Techniques are provided for video summarization, based on speaker segmentation and clustering, to identify persons and scenes of interest. A methodology implementing the techniques according to an embodiment includes extracting audio con...  
WO/2018/051931A1
In order to provide a highly reliable crossbar circuit that enables salvation of reversal of the resistive state of a resistance variable element, this semiconductor device has a configuration obtained by parallelly arranging two unit el...  
WO/2018/050960A1
A method comprising: obtaining a first clean signal (S1) and a first processed signal (S4) dependent upon audio input (24) at a first microphone (25); obtaining a second clean signal (S2) and a second processed signal (S3) dependent upon...  
WO/2018/052696A1
Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in anal...  
WO/2018/051357A1
A CDMR memory cell, includes a first bitcell which is used to store a current data level and a second bitcell which is used to store the complementary data level. When a read operation is performed, a comparator compares the data levels ...  
WO/2018/051598A1
A magnet structure (1) is provided with a first magnet unit (10) and a second magnet unit (20). The first magnet unit (10) is formed with a first magnet fixing portion (12) which includes a first surface (12a) and a first magnet (14) hav...  
WO/2018/051307A1
The present invention relates to frameworks and methodologies configured to enable support and delivery of a multimedia messaging interface, including (but not limited to) automated content generation and classification, content search a...  
WO/2018/053181A1
Systems and methods in accordance with embodiments of the invention implement optical systems incorporating lens elements formed separately and subsequently bonded to low co¬¨ efficient of thermal expansion substrates. Optical systems in...  
WO/2018/048682A1
The present invention relates to an improved sense amplifier for reading values in flash memory cells in an array. In one embodiment, a sense amplifier comprises an improved pre- charge circuit for pre-charging a bit line during a pre-ch...  
WO/2018/047736A1
A magneto-resistive device 100 is characterized in comprising first magneto-resistive elements 101a, 101b, a second magneto-resistive element 101c, a first port 109a, a second port 109b, a signal line 107, and a direct current input term...  
WO/2018/048607A1
Technology for an apparatus is described. The apparatus can include a plurality of cache memories and a cache controller. The cache controller can allocate a cache entry to store data across the plurality of cache memories. The cache ent...  

Matches 251 - 300 out of 854,772