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WO/2024/021365A1 |
Provided are a memory unit, an array circuit structure, and a data processing method. The memory unit (100) comprises at least one resistive switching device and at least two switch elements. The at least one resistive switching device c...
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WO/2024/021174A1 |
A pulse generator (10), an error check and scrub circuit, and a memory. The pulse generator (10) comprises: a delay module (11), configured to receive an ECS command signal, to perform delay processing on the ECS command signal, and to o...
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WO/2024/025175A1 |
Provided is an electronic device, comprising: a housing including an opening and a socket; a tray that can be inserted into or removed from the socket through the opening; and an actuator that generates power to remove the tray from the ...
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WO/2024/021308A1 |
Provided in the embodiments of the present disclosure are a refresh control method, a refresh control circuit and a memory. The method comprises: generating a first random number; and after the last row-hammer refresh operation is execut...
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WO/2024/025460A1 |
The present disclosure describes techniques for automatically and fast generating music for videos. The techniques comprise receiving a video from a user. The video may comprise a plurality of segments of frames. Information may be extra...
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WO/2024/025657A1 |
In a non-volatile memory system that performs programming of selected memory cells (in coordination with pre-charging and boosting of channels for unselected memory cells) and program-verify to determine whether the programming was succe...
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WO/2024/024497A1 |
A storage device according to an aspect of the present disclosure comprises: a magnetoresistive storage element that changes into at least four distinguishable resistance states; and a writing unit that changes the magnetoresistive stora...
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WO/2024/024907A1 |
A reproduction device that reproduces sound recorded on a record disc, the reproduction device comprising, in order to achieve stable sound reproduction with high sound quality, a rotating part that rotates the record disc, a container d...
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WO/2024/025659A1 |
An erase process for a group of non-volatile memory cells comprises applying doses of erasing to the group and performing erase verify between pairs of successive doses of erasing. The time needed to complete the erase process can be red...
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WO/2024/021177A1 |
A dynamic memory operation method comprises the following steps: refreshing a dynamic memory according to a preset time interval T while receiving an operation instruction in real time, and when the operation instruction is received, per...
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WO/2024/026084A2 |
A method for storage of digital information via a biopolymer includes: receiving digital information; designing a target biopolymer sequence; encoding the digital information; synthesizing the target biopolymer sequence via a layered mic...
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WO/2024/025784A1 |
Techniques for protecting non-volatile memory (NVM) from power cycle interruptions during memory operations are disclosed. A power management integrated circuit (PMIC) coupled to a memory circuit with NVM implements the various technique...
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WO/2024/025788A1 |
A device, system, and method for altering video streams to identify objects of interest is provided. A devices analyzes: media data to determine one or more visual traits of an object-of-interest (OOI); and a first video stream to determ...
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WO/2024/024781A1 |
This fluorine-containing ether compound is represented by the following formula. R1-CH2-R2[-CH2-R3-CH2-R2]x-CH2-R4 (x represents an integer of 1 or 2, R2 represents a perfluoropolyether chain, at least one of the x-number of R3 is repres...
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WO/2024/021775A1 |
Provided in the present application are a ferroelectric random access memory and an electronic device. Data storage is realized by means of a transistor and a plurality of capacitors, such that not only the capacity of the ferroelectric ...
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WO/2024/025658A1 |
An apparatus is provided that includes a block including a word line coupled to a plurality of memory cells, and a control circuit coupled to the word line. The control circuit is configured to program the plurality of memory cells by ap...
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WO/2024/025833A1 |
In at least one embodiment, a record or vinyl playback device includes a spindle clamp at a central region of the playback device and a peripheral clamp at a peripheral region of the playback device. In operation, the spindle clamp is in...
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WO/2024/025498A1 |
The invention discloses a circuit that reduces the effect of settling time-related errors by accelerating the settling time and reduces the circuit noise to a negligible level, characterized by comprising amplifier (1) wherein reference ...
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WO/2023/240521A9 |
Disclosed in the present invention are a solid state drive external enclosure and a solid state drive external enclosure set. The solid state drive external enclosure comprises an enclosure body and a substrate. The substrate is provided...
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WO/2023/231170A9 |
Provided in the present disclosure are a data processing circuit and method, and a semiconductor memory, relating to the technical field of storage. The circuit comprises: a data selection module, used for receiving write-in data and out...
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WO/2024/018297A1 |
The invention is notably directed to a device comprising a plurality of resistive memory elements. The plurality of resistive memory elements comprises a resistive material. The device is configured to apply programming pulses to a subse...
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WO/2024/019476A1 |
A method for creating an album is disclosed. The method for creating an album, according to an embodiment of the present invention, comprises the steps of: receiving an input for selecting content or an artist to be included in an album;...
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WO/2024/017077A1 |
A memory device, having a plurality of first-word-lines, each first-word-line having a first portion, a second portion, and a third portion; a plurality of second-word-lines, each second-word-line having a first portion, a second portion...
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WO/2024/019825A1 |
An apparatus is provided that includes a block of memory cells and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by determining a firs...
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WO/2024/020497A1 |
System, process and device configurations are provided for interface customized generation of gaming music. A method can include generating a musical accompaniment for electronic gaming by way of an interface. An interface is provided fo...
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WO/2024/016864A1 |
A processor, an information acquisition method, a single board and a network device, which relate to the technical field of computers. The processor comprises a control module (101), a first register (102) and a cache (103), and the proc...
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WO/2024/016855A1 |
Provided are a method and apparatus for determining a memory fault repair mode, and a storage medium. The method comprises: acquiring information of a plurality of row faults, wherein the information of the row faults comprises the seque...
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WO/2024/018556A1 |
A memory device in which, on a substrate in a plan view, a page is configured from a plurality of memory cells arranged in a row direction, and a plurality of the pages are arranged in a column direction, the memory device being characte...
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WO/2024/016939A1 |
A chip self-checking method and a chip. The chip comprises a self-checking module and a storage module. The chip self-checking method comprises: a self-checking module receives externally inputted address configuration parameter informat...
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WO/2024/016732A1 |
Provided in the present invention is a method for preparing a top electrode of a magnetic memory, the method comprising: providing a bottom structure, wherein the bottom structure has a patterned magnetic tunnel junction, and the top of ...
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WO/2024/016426A1 |
A method and apparatus for testing a memory chip, a device, and a storage medium. The method comprises: grouping and sequentially enabling a plurality of word lines in a storage array of a memory chip to be tested, wherein a time interva...
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WO/2024/016792A1 |
The present disclosure provides a memory chip anti-miswrite control method and apparatus, and an electrical device. The method comprises: determining whether a main control chip has a write demand on a memory chip; if the main control ch...
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WO/2024/016557A1 |
A shift register circuit and an electronic device, related to the technical field of integrated circuits. The shift register circuit comprises a number m of cascaded flip-flops, clock input terminals of at least some of the flip-flops am...
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WO/2021/194534A9 |
Methods and apparatus for managing power in data storage devices implementing non-volatile memory (NVM) sets are provided. One such apparatus includes a NVM including a first NVM set and a second NVM set, first backend logic circuitry co...
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WO/2024/014081A1 |
The present invention achieves a memory cell in which magnetization can be reversed on the basis of voltage driving without providing a selector element to the memory cell.　This storage device comprises: a memory cell provided with a m...
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WO/2024/011407A1 |
The present disclosure provides a memory cell and a preparation method therefor, a memory, and an information storage method. The memory cell comprises: a piezoelectric substrate layer, a first electrode and a second electrode being resp...
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WO/2024/015046A1 |
In example embodiments described herein are various features for a dual cassette. In one embodiment, a push plate catch and release mechanism is employed that can prevent movement of the push plate when movement of the push plate is not ...
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WO/2024/012375A1 |
The present disclosure provides an MTP memory power supply system and power supply method. A power source voltage generated by a power source is firstly processed by a voltage generator to form a first voltage, and a lifting voltage is t...
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WO/2024/012123A1 |
Provided in the present application are a storage control circuit, a memory, a repair method for the memory, and an electronic device. The storage control circuit is used for controlling a storage array in the memory. The storage array c...
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WO/2024/016015A1 |
A method for fabricating a forming-free resistive random-access memory (RRAM) device is provided. The method includes: fabricating an RRAM cell and annealing the RRAM cell. The RRAM cell includes: a bottom electrode, a switching oxide la...
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WO/2024/011924A1 |
The present disclosure provides a data processing method and apparatus, a memory controller, a device, and a medium. The memory controller which is used for a memory is configured to work in at least one mode comprising a software and ha...
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WO/2024/013604A1 |
Provided is a semiconductor device with a novel configuration. This semiconductor device has: a first computing device that has registers, and a second computing device that has memory circuits, layer selecting circuits, and a computing ...
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WO/2024/014340A1 |
This method for manufacturing a mother glass sheet includes a collection step P2 for collecting a mother glass sheet 8 for inspection, and a measurement step for measuring the shape accuracy of the mother glass sheet 8 for inspection, wh...
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WO/2023/115331A9 |
A shift register, used for a display substrate, the display substrate comprising multiple rows of sub-pixels. The shift register is electrically connected to at least one row of sub-pixels, and is configured to transmit a scanning signal...
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WO/2024/007544A1 |
A memory cell, an array read-write method, a control chip, a memory, and an electronic device, relating to the technical field of semiconductors. The memory cell comprises: a first transistor (TR_R) and a second transistor (TR_W); the fi...
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WO/2024/009886A1 |
According to the present invention, an insulating layer has first and second main surfaces. A conductor layer is provided on the first main surface. A metal thin film is provided on the second main surface and has a third main surface fa...
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WO/2024/007378A1 |
Provided in the embodiments of the present disclosure are a data receiving circuit, a data receiving system, and a storage apparatus. The data receiving circuit comprises: a first amplification module, which is configured to receive a da...
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WO/2024/010347A1 |
The present technology relates to a high-speed and high-energy-efficiency magnetic tunnel junction element. The high-speed and high-energy-efficiency magnetic tunnel junction element of the present technology comprises: a main pinned lay...
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WO/2024/010988A1 |
Provided is a method and apparatus for digital image watermarking. In the method and apparatus, a computer system receives a first image and receive information for embedding in the first image. The computer system preprocesses the first...
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WO/2024/009384A1 |
A semiconductor device according to an embodiment of the present invention, which is capable of outputting data at high speed despite being relatively inexpensive, is provided with: a plurality of memories that each include a strobe sign...
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