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Patent Searching and Data


Matches 251 - 300 out of 856,854

Document Document Title
WO/2018/234920A1
A memory device includes a non-volatile random access memory. The non-volatile memory includes a suspect bit register configured to store addresses of bits that are determined to have had errors. The non-volatile memory further includes ...  
WO/2018/231423A1
Systems, apparatuses, and methods related to dynamic random access memory (DRAM), such as finer grain DRAM, are described. For example, an array of memory cells in a memory device may be partitioned into regions. Each region may include ...  
WO/2018/230466A1
Provided is a ferromagnetic tunnel junction which, as a tunnel barrier layer disposed between a first magnetic layer and a second magnetic layer, is an oriented crystal body having a laminated structure of a first insulating layer and a ...  
WO/2018/231410A1
A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) t...  
WO/2018/229332A1
An arrangement (100), optionally comprising one or more network accessible servers, for searching for digital video material, wherein the arrangement comprises at least one processor (102) configured to receive a number of video items: s...  
WO/2018/227901A1
A vertically magnetized MTJ device and an STT-MRAM. The vertically magnetized MTJ device comprises a reference layer (2), an insulation barrier layer (3), a free layer (4), an enhancing layer (5), a demagnetization coupling layer (6) and...  
WO/2018/231299A1
A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel gradient near the select gate transistors is reduced when...  
WO/2018/231981A1
A method and apparatus for quantitatively characterizing performance of a laser steering galvanometer mirror directs a laser beam from a calibration "sensor" onto a side region of the mirror to directly determine rotational positioning, ...  
WO/2018/231482A1
Logic integrated with a memory and related methods for performing background functions are provided. A method in a memory includes, in response to a request from a host separate from the memory, initiating processing of a background func...  
WO/2018/227408A1
A hard disk box, comprising a housing (10), a fixing support (20), shock absorbers (30), and a lower cover (40); the outer sides of two opposite first side plates (22) of the fixing support (20) are respectively provided with one shock a...  
WO/2018/231305A1
Systems and methods are described for predicting an endurance of groups of memory cells within a memory device, based on current characteristics of the cells. The endurance may be predicted by processing historical information regarding ...  
WO/2018/231298A1
A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation. A pre-charge operation occurs in which a channel voltage is increased to a positive level. This reduces a channel gradient w...  
WO/2018/231431A1
Methods and devices for compensating for detected motion when capturing an image may include determining at least one of a global movement of an imaging device and a local movement of one or more objects in a scene captured by the imagin...  
WO/2018/229590A1
Provided is a semiconductor device that performs error detection and correction on multi-valued data. This semiconductor device comprises a first gray code conversion circuit, a second gray code conversion circuit, a gray code reverse co...  
WO/2018/230366A1
The present technique relates to a signal processing device and method, and a program for enabling a decrease in processing load while ensuring safety. The signal processing device is provided with: a control unit which acquires designat...  
WO/2018/231556A1
An integrated circuit comprising an array of logic tiles, arranged in an array of rows and columns. The array of logic tiles includes a first logic tile to receive a first external clock signal wherein each logic tile of a first pluralit...  
WO/2018/231399A1
A memory device and method of operating the same are disclosed. Generally, the device includes an array of Ferro-electric Random Access Memory cells. Each cell includes a first transistor coupled between a bit-line and a storage node (SN...  
WO/2018/227878A1
A chip burner for burning a chip, comprising: a base, on which a burning tray is fixed; a plurality of burning grooves which are fixed on the burning tray; a plurality of latching members, each of the plurality of latching members being ...  
WO/2018/231313A1
Apparatuses, systems, methods, and computer program products are disclosed for a multicore on-die memory controller 150. An integrated circuit device 123, 212, 700 includes an array of non-volatile memory cells 200 and a microcontroller ...  
WO/2018/227174A1
A data security apparatus includes an analog component. The analog component operates internally with a high degree of entropy. This high degree of entropy resides in the interactions between its internal components in response to an ext...  
WO/2018/226478A1
Methods, systems, and devices for dual mode ferroelectric memory cell operation are described. A memory array or portions of the array may be variously operated in volatile and non-volatile modes. For example, a memory cell may operate i...  
WO/2018/225993A1
According to an embodiment, a phase-change memory device comprises: an upper electrode and a lower electrode; a phase-change layer in which a crystal state thereof is changed by heat supplied by the upper electrode and the lower electrod...  
WO/2018/226280A1
Disturbs are reduced during programming and read operations for drain-side memory cells in a string by controlling dummy word line portions separately in selected and unselected sub-blocks. One or more of the dummy word line layers are s...  
WO/2018/224928A1
A magnetic tunnel junction (MTJ) storage element includes a reference layer, a tunnel barrier and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The reference layer has a fixed magnetization direct...  
WO/2018/226179A1
The present invention relates to a multi-layer structure with a [NiMn / Co] content (Si/Pt (tPt) /Ni45Mn55 (tAFM) /Co (tFM)/ Pt (30A) ) formulation in which the spontaneous exchange shift effect (SEB) is observed. In this invention, a mu...  
WO/2018/226474A1
Methods, systems, and devices for time-based access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state...  
WO/2018/226477A1
Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic...  
WO/2018/226021A1
One embodiment provides a method comprising identifying a product placement opportunity for a product in a frame of a piece of content during playback of the piece of content on a display device. The method further comprises determining ...  
WO/2018/223837A1
Disclosed are a music playing method and a related product. The method comprises: acquiring user habit data for music playing; determining a playing moment according to the user habit data; acquiring a user mood parameter and/or an envir...  
WO/2018/224726A1
A method including capturing, by a low latency monitoring device (432), content visualized in video rendering mode, capturing at least one parameter modified (474) in the video rendering mode, determining at least one correction update m...  
WO/2018/223834A1
A shift register unit and a driving method thereof, a gate driving circuit, and a display device in the technical field of displays. The shift register unit comprises a control subcircuit (20) and a noise reduction subcircuit (30). When ...  
WO/2018/226692A1
A method and system for tracking movements of objects in a sports activity are provided. The method includes matching video captured by at least one camera with sensory data captured by each of a plurality of tags, wherein each of the at...  
WO/2018/225725A1
Provided is a glass for an information recording medium substrate, said glass being an an amorphous glass which has, in terms of mol%, an SiO2 content of 55-68%, a B2O3 content of 0-5%, an Al2O3 content of 1-14%, an MgO content of 8-23%,...  
WO/2018/224811A1
The present techniques generally relate to methods, systems and devices for operation of memory device. In one aspect, bit positions of a portion of a memory array may be placed in a first value state. Values to be written to the bit pos...  
WO/2018/224911A1
The present invention provides a semiconductor device having a large storage capacity per unit area. Specifically provided is a semiconductor device having memory cells, the memory cells being provided with: a first conductor; a first in...  
WO/2018/226586A1
A method includes generating a bias signal from a first device, and applying the bias signal to a second device, the first device having (a) a superconducting trace and (b) a superconducting quantum interference device (SQUID), in which ...  
WO/2018/225386A1
An optical device according to an embodiment of the present disclosure is a device that performs at least one of writing and deleting of information on a reversible recording medium. The optical device is provided with: a plurality of la...  
WO/2018/224929A1
A magnetic tunnel junction (MTJ) storage element includes a reference layer, a tunnel barrier and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The reference layer has a fixed magnetization direct...  
WO/2018/220356A1
The present techniques generally relate to fabrication of correlated electron materials (CEMs) devices used, for example, to read from a resistive memory element or to write to a resistive memory element. In embodiments, by limiting curr...  
WO/2018/219886A1
The proposed invention relates to a method for situation-dependent storage of data of a system, in which data of the system is detected, is amalgamated in at least one data block (9, 9a) and is stored in a volatile memory, and in which, ...  
WO/2018/220220A1
The present invention relates to an electroless nickel alloy plating bath comprising nickel ions; further reducible metal ions selected from the group consisting of molybdenum ions, rhenium ions, tungsten ions, and mixtures thereof; at l...  
WO/2018/222582A1
A magnetoresistive dynamic random access memory (MDRAM) cell is described. A hybrid memory cell includes a first transistor having a first source/drain electrode coupled to a charge storage node and a gate of a second transistor. A first...  
WO/2018/218531A1
An EEPROM programming system and an EEPROM programming method. The EEPROM programming system (1) comprises an upper computer (11), an EEPROM programmer (12) and a chip programming seat (13). The upper computer (11) is used for receiving ...  
WO/2018/221293A1
Provided is a configuration that converts MMT format data to MPEG-2TSV format data and records the result to a medium, and allows copy control that complies with original copy control information. MMT format data for which copy control i...  
WO/2018/218659A1
Provided are a method and device for a page being read to play back background sound, comprising: when a page being read receives a trigger instruction for playing back background sound, calling a corresponding background sound access in...  
WO/2018/218886A1
A shift register, a gate driving circuit and a display device. The shift register comprises: a first shift register unit, a second shift register unit, a pull-down control subcircuit (20) and a pull-down subcircuit (30); the first shift ...  
WO/2018/222586A1
Aspects for reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells are disclosed herein. An exemplary SRAM strap cell includes a P-type doped well (Pwell) tap electrically coupled to a first supply rail ...  
WO/2018/218731A1
A potential transfer circuit (103, 300), a driving method therefor, and a display panel thereof. The potential transfer circuit (103, 300) comprises: a core circuit (310) configured to provide an image signal; a control unit (320) config...  
WO/2018/220846A1
The present invention provides a semiconductor module capable of improving a bandwidth between a logic chip and a RAM. According to the present invention, a semiconductor module 1 is provided with: a logic chip; a pair of RAM units 30 ea...  
WO/2018/221292A1
Provided is a configuration that allows reproduction permission age information corresponding to recorded content of a medium to be recorded, and allows reproduction control that is based on age to be performed at the time of reproductio...  

Matches 251 - 300 out of 856,854