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Patent Searching and Data


Matches 151 - 200 out of 846,066

Document Document Title
WO/2017/045380A1
A shift register unit, and driving method, gate driving circuit, and display device thereof. The shift register unit comprises an input unit (110), an output unit (120), a reset unit (130), a first control unit (140) and a second control...  
WO/2017/046671A1
Single ended bitline current sense amplifier for SRAM applications. The present disclosure relates to current sense read amplifier for use as a read amplifier in a memory arrangement of memory cell groups, wherein in each of the memory c...  
WO/2017/048030A1
A device and a method for playing a double sound source for three-stage vocal language learning are disclosed. The device comprises: a sound source database for respectively storing a vocal language sound source and a background sound so...  
WO/2017/048441A1
A memory subsystem enables satisfying refresh needs for a memory device with hidden refreshes performed by the memory device in response to Activate commands, and external refreshes to make up a difference between the number of hidden re...  
WO/2017/047272A1
This semiconductor storage device of the present disclosure is provided with: a block which has a plurality of pages; and a controller which controls writing, erasing and reading of data, wherein each page has a plurality of memory cells...  
WO/2017/048293A1
An example device in accordance with an aspect of the present disclosure includes a plurality of first sense circuits of a first type and at least one second sense circuit of a second type. The first sense circuits are to perform first-l...  
WO/2017/047737A1
In the present invention, a data storage medium is provided with a structure that has protrusions and recesses, said structure being in a storage region established on a first surface of a quartz glass substrate. The storage region inclu...  
WO/2017/047725A1
The same digital data is recorded at a high degree of integration on a plurality of media able to durably hold information over a prolonged period of time. A fine graphic pattern indicating data bit information is drawn and developed by ...  
WO/2017/046991A1
The present invention provides a perpendicular magnetic recording medium that contains a magnetic recording layer having a desired film thickness, while having an expected reduction in Tc and maintaining conventional magnetic properties....  
WO/2017/045720A1
The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a r...  
WO/2017/045077A1
A system and method for capturing and recording audio suitable for subsequent reproduction in a 360 degree, virtual and augmented reality environment is described. It includes recording audio input from a plurality of audio sensors arran...  
WO/2017/048440A1
Aspects of a memory and method for accessing the memory are disclosed. The memory includes a plurality of memory cells configured to support a read and write operation in a memory cycle in a first mode and a write only operation in the m...  
WO/2017/046850A1
A semiconductor memory device according to an embodiment of the present invention includes: a memory cell array including memory cells connected to a bit line; and a control circuit for writing data, including a first stage and a second ...  
WO/2017/048229A1
Described is an apparatus which comprises: a first transistor; a second transistor having a first terminal coupled to a first terminal of the first transistor; a first conductor coupled to a second terminal of the second transistor; a ma...  
WO/2017/048377A1
A device includes a redundant region of a magnetoresistive random access memory (MRAM) array that includes first memory cells. The device includes a data region of the MRAM array that includes second memory cells. The device includes a f...  
WO/2017/048326A1
A method and process for video recording on a mobile device that simultaneously records, syncs, and combines two captured video streams into one resulting video recording enabling a user to video record an event, be visually immersed in ...  
WO/2017/046638A1
A solid-state memory device has memory devices and memory sticks. Each memory stick is coupled to a subset of the memory devices. A controller provides parallel access to the memory devices through the memory sticks to provide a virtuali...  
WO/2017/045390A1
A shift register, gate driving circuit and display device. The shift register comprises: input module (1), a first control module (2), a second control module (3), a first output module (4), and a second output module (5). By mutual coop...  
WO/2017/048228A1
In one example a system includes a memory, and at least one memory controller to: detect a failed first memory location of the memory, remap the failed first location of the memory to a spare second location of the memory based on a poin...  
WO/2017/048509A1
Shared source line magnetic tunnel junction (MTJ) bit cells (300A) employing uniform MTJ connection patterns for reduced area are disclosed. In one aspect, a two (2) transistor, two (2) MTJ (2T2MTJ) bit cell includes a shared source line...  
WO/2017/048337A1
A storage device with a charge trapping (CT) based memory may include improved data retention (DR) performance. The CT memory may be 3D memory that uses a charge storage layer for storing charge may have unique data retention behavior. M...  
WO/2017/048411A1
The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to dete...  
WO/2017/044339A1
Systems and methods are disclosed for managing temperature in a data storage device. A data storage device includes non-volatile solid-state memory, a temperature sensor, a heating device, and a controller. The controller is configured t...  
WO/2017/044251A1
The present invention relates to a flash memory device that uses dummy memory cells as source line pull down circuits.  
WO/2017/041227A1
System and method can support three-dimensional display. The system can receive a plurality of image frames, which are captured by an imaging device on a movable object. Furthermore, the system can obtain state information of the image d...  
WO/2017/044095A1
Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a first spin current; a first layer configured to convert the first spin current to a second charge current via spin orbit c...  
WO/2017/044338A1
Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array....  
WO/2017/042900A1
Provided is an optical information recording technique in which change in phase difference between signal light and reference light during recording is corrected during recording to record a high quality hologram, and thereby phase multi...  
WO/2017/044165A1
Sense circuits in a memory device can be pre-charged to different levels in a sensing process to reduce the amount of time used for sensing. For example, in a program operation, a memory cell is in a fast programming mode until its thres...  
WO/2017/044695A1
An apparatus includes acoustic equipment and an enclosure to support the acoustic equipment. The enclosure includes a front cover member, a middle cover member, a back cover member, and a hinge to connect the front cover member to the ba...  
WO/2017/042587A1
The present techniques generally relate to correlated electron switches that are capable of asymmetric set or reset operations.  
WO/2017/044220A1
Embodiments describe techniques and configurations for an apparatus including a three-dimensional (3D) memory array having a plurality of strings of memory cells, where individual strings may have memory cells that correspond to differen...  
WO/2017/043149A1
The present invention makes it possible to perform highly reliable data reading by maintaining a sufficient margin that separates resistance states in a resistance variable memory. The memory includes a plurality of memory cells with eac...  
WO/2017/043111A1
According to one embodiment, a semiconductor memory device comprises a first bank and a second bank. Each of the first bank and the second bank comprises a memory cell having a variable resistor element, a reference cell, a sense amplifi...  
WO/2017/044167A1
Methods and systems are provided where non-volatile solid state memory may include selected memory cells coupled to a selected word line and proxy memory cells coupled to a proxy word line. The selected memory cells may be non-adjacent t...  
WO/2017/044110A1
Example embodiments relate to securing data with memristors. The examples disclosed herein provide a memristor where the memristor is in one of a first resistance state and a second resistance state. An encryption is applied to the memri...  
WO/2017/044233A1
A disclosed example includes selectively precharging first bitlines of first multi-level cell (MLC) memory cells of a wordline without precharging second bitlines of second MLC memory cells of the wordline during a program verify. First ...  
WO/2017/043105A1
According to one embodiment, a memory- includes a bit line connected to a memory cell; and a read circuit to execute reading of data from the memory cell. The read circuit includes a first circuit having a first input terminal and detect...  
WO/2017/043378A1
In the transmission of multiple kinds of LPCM signals/compressed digital audio signals, the present invention switches these signals and makes it possible to reproduce audio from these signals in a satisfactory manner. Digital audio sign...  
WO/2017/044047A1
The present application relates to a computational active Solid-State Drive(SSD) storage device, comprising: an active interface configured for data communication with one or more host machines, the active interface being configured to a...  
WO/2017/039608A1
A nonvolatile memory cell includes a volatile selector electrically coupled in series with a nonvolatile resistance memory device. The nonvolatile resistance memory device may be a switching material sandwiched between a first bottom ele...  
WO/2017/039948A1
An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory devic...  
WO/2017/037983A1
Provided is an electronic apparatus capable of protecting a plurality of HDD units from shocks without requiring size increase of the apparatus. According to one embodiment of the present art, an electronic apparatus is provided with a p...  
WO/2017/038201A1
[Problem] The present invention provides an information recording medium glass substrate production method, the glass substrate having a very low Ra and being able to sufficiently support higher recording capacity and higher accuracy, wh...  
WO/2017/036113A1
Circuits (300, 400), devices, methods for decision feedback equalization are described. A decision feedback circuit (300) can include a plurality of decision feedback equalizer (DFE) branches, each DFE branch including: a pre-computation...  
WO/2017/036293A1
A dynamic random access memory for a three-level unit, and a method for reading same. The dynamic random access memory (DRAM) for a three-level unit stores three voltage levels (0, VDD/2, VDD) on a plurality of storage units. A selected ...  
WO/2017/039203A1
The present invention provides an asynchronous serial communication system and method and comprises a semiconductor device, which has two terminals and receives a voltage required for operation from transmitted data through one terminal,...  
WO/2017/039781A3
Systems and methods supporting high performance real time pattern recognition by including time and regional multiplexing using high bandwidth, board-to-board communications channeis, and 3D verticai integration. An array of processing b...  
WO/2017/039826A2
Image-hosted data encryption implementations are presented that encrypt and decrypt data within a host image. A bit stream representing a data item and a host image are accessed. The host image has pixels which include one or more color ...  
WO/2017/038018A1
Provided is an opening/closing mechanism for a rotary cover that can stop a transparent cover that rotates within a plane at a suitable closed cover position. The opening/closing mechanism for a rotary cover is provided with a transparen...  

Matches 151 - 200 out of 846,066