Login| Sign Up| Help| Contact|

Patent Searching and Data


Matches 151 - 200 out of 855,940

Document Document Title
WO/2018/181921A1
The present invention enables improvement of a set-forming yield while preventing insulation breakdown of a rectifying element when being set. In a plurality of switching cells, terminals on one side of two variable resistance elements a...  
WO/2018/182848A1
Systems and methods are disclosed for reducing memory power consumption via pre-filled dynamic random access memory (DRAM) values. One embodiment is a method for providing DRAM values. A fill request is received from an executing program...  
WO/2018/182961A1
A circuit (200) including an output node (OUT) and a cross-coupled pair of semiconductor devices (204, 214) configured to provide, at the output node, an output signal in a second voltage domain (VDDH) based on an input signal in a first...  
WO/2018/180228A1
A memory device according to an embodiment of the present disclosure comprises a memory cell array which is configured such that, when, of a plurality of memory cells, a plurality of first memory cells of which corresponding fourth wires...  
WO/2018/179193A1
Provided are: a memory element that is capable of efficiently storing, as a selection value, a continuous quantity or multi-valued discrete quantity; and a method for driving a memory element. A memory element (10) has a structure in whi...  
WO/2018/178644A1
There is provided a system comprising: a storage device having a storage portion comprising a plurality of bitcells coupled to respective first signal lines and second signal lines and control logic to alter a memory state of the plurali...  
WO/2018/181901A1
Provided is a cleaning solution composition which: does not damage SiO2, Si3N4, Si, etc., forming a layer on the substrate surface, when cleaning a surface of a semiconductor substrate or a glass substrate; can be used under processing c...  
WO/2018/178720A1
A switching resistor has a low resistance state and a high resistance state. The switching resistor comprises a dielectric layer disposed between a first electrode and a second electrode. The switching resistor further comprises a textur...  
WO/2018/176388A1
Various embodiments are generally directed to techniques to maintain confidentiality of non-volatile memoryin a computer system through power state changes, such as, between a hibernation state and an awake state, for instance. Some embo...  
WO/2018/182994A3
The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset ...  
WO/2018/182994A2
The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset ...  
WO/2018/178910A1
An electronic device structure and a cascaded serial communication scheme that make it possible to avoid pre-installation programming operations in devices comprising two or more integrated circuits. At least one of the integrated circui...  
WO/2018/182669A1
Techniques are disclosed for forming and using a "racetrack memory" (also referred to as a "shift register") that reads and writes data to magnetic domains within a ferromagnetic conductor using the Rashba Bychkov ("RB") effect. The RB e...  
WO/2018/173780A1
The present invention implements a configuration for reproducing block encrypted MMT format data with a timestamp applied thereto. An MMT format stream file and a reproduction control information file are created and recorded on a medium...  
WO/2018/175129A1
The present disclosure includes apparatuses and methods for in data path compute operations. An example apparatus includes an array of memory cells. Sensing circuitry is selectably coupled to the array. A plurality of shared input/output...  
WO/2018/175001A1
A system and method are disclosed for performing address fault detection in a flash memory system. An address fault detection array is used to confirm that an activated word line or bit line is the word line or bit line that was actually...  
WO/2018/175598A2
An integrated circuit enabling the selection of a circuit is described. The integrated circuit comprising a plurality of redundant circuits (512, 514) providing a predetermined function; a voltage sensor (212) coupled to receive a refere...  
WO/2018/175136A1
A write driver is provided that includes a first write driver inverter that inverts a data signal to drive a gate of a second write driver transistor. The write driver transistor has a terminal coupled to a bit line and another terminal ...  
WO/2018/171133A1
A shift register unit, a gate driving circuit comprising the shift register unit, and a driving method applied to the shift register unit. The shift register unit comprises an input module (101), an output module (102), an output reset m...  
WO/2018/175093A1
A write precharge period for a pseudo-dual-port memory is initiated by an edge (rising or falling) of a read precharge signal. The same edge type (rising or falling) of a write precharge signal signals the end of the write precharge period.  
WO/2018/175634A1
Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first die including a first switch circuit that receives a plurality of data signals, and further provides the plur...  
WO/2018/173513A1
The present invention provides a nonvolatile semiconductor storage device that facilitates better miniaturization than was previously possible. A nonvolatile semiconductor storage device 1 has a structure wherein memory cells 3a (3b) are...  
WO/2018/175089A1
A stack of MTJ layers is provided on a substrate comprising a bottom electrode, a pinned layer, a tunnel barrier layer, a free layer, and a top electrode. The MTJ stack is patterned to form a MTJ device wherein sidewall damage is formed ...  
WO/2018/173851A1
A storage device of the present disclosure has: multiple first wirings extending in a first direction and including multiple first select lines and multiple second select lines; multiple second wirings extending in a second direction tha...  
WO/2018/174874A1
Memory devices in which a memory cell includes a thin film select transistor and a capacitor (1TFT-1C). A 2D array of metal-insulator-metal capacitors may be fabricated over an array of the TFTs. Adjacent memory cells coupled to a same b...  
WO/2018/175121A1
The present disclosure includes apparatuses and methods for in-memory data switching networks. An example apparatus includes an array of memory cells. Sensing circuitry is selectably coupled to the array of memory cells. An input/output ...  
WO/2018/173615A1
In a semiconductor integrated circuit using power gating, a control input signal (SLP) is propagated to a power switch (10) via a propagation path (11) and propagated to a power switch (20) via a propagation path (21). A return determina...  
WO/2018/175613A1
Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes a signal receiver that receives information signal; a control circuit that provides a plurality of control signals; and a si...  
WO/2018/175232A1
Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circui...  
WO/2018/167948A1
A content playback device in which the content playback device, which is a parent device, distributes content data to other content playback devices, which are child devices, the content playback device and the other content playback dev...  
WO/2018/169509A1
An image capturing device may include a recording circuit configured to record multimedia data of a field of view of the image capturing device, a receiving circuit configured to receive a wireless signal from a wireless sensor, a locati...  
WO/2018/168198A1
Provided is a semiconductor storage device which is able to be produced with less cost. A semiconductor storage device according to one embodiment of the present invention is provided with a first substrate, a first element layer that is...  
WO/2018/169335A1
An STT-MRAM device according to the present embodiment comprises: a spin transfer torque magnetic random access memory (STT-MRAM) memory array which includes a data storage unit for storing data, a failed area address storage unit for st...  
WO/2018/167651A1
Systems, devices and processes improve the reliability of wireless communications within a video production system by providing a map or other graphical interface showing the relative locations of video capture devices, access points and...  
WO/2018/167706A1
The invention relates to a system for automatically creating a soundtrack, comprising a camera device (1, 1') for recording a user- generated video, at least one wearable sensor (3, 3'), and a control unit (2, 2') in communication with t...  
WO/2018/166215A1
A shift register unit (UN), an array substrate and a display device, belonging to the field of displays. In the shift register unit (UN): the gate electrode of a first transistor (M1) is connected to a third node (NET1), wherein one of t...  
WO/2018/167951A1
This content playback device is provided with: a playlist acquisition means which acquires playlist information that indicates a playback order of one or a plurality of pieces of content; a playback necessary condition acquisition means ...  
WO/2018/169732A1
An electronic device is described that displays and enables interaction with custom user interface ("UI") elements. The electronic device may include a display, an actuatable button, and controls enabling user selection of individual cus...  
WO/2018/166201A1
A data reading method, low-voltage detection logic circuit, an integrated circuit and a chip. The data reading method comprises: upon receiving a request to read data within a non-volatile memory (NVM), reading a pre-burning area return ...  
WO/2018/166081A1
The present invention relates to a headset capable of being used for panoramic photography. The headset comprises a left earpiece body and a right earpiece body, wherein the left earpiece body is provided with a left camera on the side f...  
WO/2018/169676A1
A magnetic tunnel junction (MTJ) is disclosed wherein first and second interfaces of a free layer (FL) with a first metal oxide (Hk enhancing layer) and second metal oxide (tunnel barrier), respectively, produce perpendicular magnetic an...  
WO/2018/163658A1
In order to provide a magnetic recording medium in which the average particle diameter and the particle diameter distribution are reduced, the present invention provides a magnetic recording medium that has an applicable magnetic propert...  
WO/2018/161527A1
Provided are a shift register (100), a gate-driver circuit, a display panel, and a driving method. The shift register (100) comprises an input circuit (110), an output circuit (130), a pull-up node pull-down circuit (140), a first pull-d...  
WO/2018/163938A1
The purpose of the present invention is to increase the fall rate of a gate signal output from a shift register. A signal immediately after an output from a shift register (12a) in a shift resister block (12) turns on a reset switching e...  
WO/2018/163618A1
[Problem] To provide a magnetic memory with which the occurrence of inversion errors can be suppressed and stable recording can be achieved. [Solution] A magnetic memory comprises: a spin orbit layer in which spin-polarized electrons are...  
WO/2018/161561A1
A shift register (200) includes a first input circuit (10), a second input circuit (20), and a pull-up transistor (M3). The first input circuit (10) is coupled to a first input terminal (IN_1) and a first pull-up node (PU_1), and configu...  
WO/2018/161806A1
A shift register comprises: a first generation circuit (2) generating a first clock signal and providing the same to a shift register logic circuit (0); a second generation circuit (4) generating a second clock signal and providing the s...  
WO/2018/163737A1
[Problem] To provide a control circuit that is capable of reliably generating a reference potential while suppressing an increase in power consumption or an increase in cost. [Solution] Provided is a control circuit that, when generating...  
WO/2018/162873A1
An apparatus for changing a record comprising a record changing fork comprising first and second spaced apart tines arranged in a record plane and extending from a fork base to a fork mouth, each tine comprising a groove extending from t...  
WO/2018/163985A1
A scanning line drive circuit 10 constructed from a cascade of single circuits 11 operates in accordance with eight-phases of clock signals CK1 through CK8 that vary between a high-level voltage VGH and a low-level voltage VSS1. A single...  

Matches 151 - 200 out of 855,940