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Patent Searching and Data


Matches 151 - 200 out of 858,320

Document Document Title
WO/2019/133223A1
A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. Further, the method comprises writing a seco...  
WO/2019/133396A1
Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the firs...  
WO/2019/132822A1
The invention relates to a universal communication module for establishing connections between electronic devices. The invention relates to a system for communicating with other systems via a communication line connected to a USB (Univer...  
WO/2019/130144A1
Provided is a novel storage device. The storage device has a plurality of memory cells arranged in a matrix. Each memory cell has a transistor and a capacitance element. Each transistor has a first gate and a second gate which have regio...  
WO/2019/133198A1
Devices and techniques for managing partial superblocks in a NAND device are described herein. A set of superblock candidates is calculated. Here, a superblock may have a set of blocks that share a same position in each plane in each die...  
WO/2019/131393A1
Provided are: a position sensing element which is provided with an exchange coupled film that has a large exchange coupling magnetic field; and a position sensor which has good sensing accuracy in a high temperature environment. A positi...  
WO/2019/133239A1
Methods and devices for techniques for precharging a memory cell are described. Precharging a memory cell while the memory cell is coupled with its digit line may reduce a total duration of an access operation thereby reducing a latency ...  
WO/2019/133233A1
A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method further comprises writing a secon...  
WO/2019/133243A1
Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory ce...  
WO/2019/133202A1
Apparatuses, methods, and devices that can be utilized to provide temperature-based memory operations are described. One or more apparatuses can include a memory device and a controller coupled to the memory device and configured to: det...  
WO/2019/133868A1
An STT-MRAM device incorporating a multiplicity of MTJ junctions is encapsulated so that it dissipates heat produced by repeated read/write processes and is simultaneously shielded from external magnetic fields of neighboring devices. In...  
WO/2019/131025A1
This resistance-change type nonvolatile storage device has: a memory cell array that has a plurality of memory cells (10); a writing circuit that executes writing in the memory cells (10); and a control circuit. Each of the memory cells ...  
WO/2019/133244A1
A memory device for storing data is disclosed. The memory device comprises a memory bank comprising a plurality of addressable memory cells configured in a plurality of segments wherein each segment contains N rows per segment, wherein t...  
WO/2019/133325A1
Methods, systems, and devices for polarity-conditioned memory cell write operations are described. A memory cell may be written with a logic state by performing a write operation that includes applying a first write voltage across the me...  
WO/2019/133638A1
Aspects of the technology described herein allow a user to add tags to a video as the video is being recorded. The tags can be added by capturing the user's voice as the video is recorded. Aspects can be performed by a head-mounted displ...  
WO/2019/133258A1
Described embodiments relate to look up table operations implemented in a digital data processor (100). A look up table read instruction recalls data elements of a specified data size from table(s) and stores recalled data elements in su...  
WO/2019/133485A1
A transistor structure, according to one embodiment, includes: an epitaxially grown vertical channel, a word line which surrounds a middle portion of the vertical channel, and a p-MTJ sensor coupled to a first end of the vertical channel...  
WO/2019/133116A1
Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refres...  
WO/2019/130595A1
The audio equipment is provided with: a beat position acquisition part (441) for analyzing beat positions in music data being played back or for acquiring an analysis result; and a beat position display part (442) for displaying, in the ...  
WO/2019/131967A1
Provided is an adhesive sheet having excellent moisture resistance and having suppressed gas generation. This sheet body is laminated, having an adhesive layer on at least one surface thereof. Based on a modified MOCON method, the sheet ...  
WO/2019/133340A1
A circuit and method for boosting the voltage input to the gate of a MOSFET switch used in an electronic rodent trap is provided. By boosting the voltage to the gate, the MOSFET can be fully turned on to activate an effective killing cyc...  
WO/2019/131968A1
Provided is an adhesive composition capable of exhibiting excellent moisture resistance. As a result of the present invention, an adhesive composition is provided that includes a polymer A and a polymer B that is different from polymer A...  
WO/2019/133534A1
A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isola...  
WO/2019/130286A1
An audio processing system may include at least one memory configured to maintain a plurality of audio signal processing algorithms and audio components, and a server having a processor. The processor may be configured to present an inte...  
WO/2019/130592A1
This acoustic apparatus is provided with a display section (43), and a mask section (44) covering a part of the display section (43), the display section (43) has a first display region (431A) capable of freely displaying an image, and a...  
WO/2019/133211A1
In certain aspects of the disclosure, an apparatus, comprises a first memory having a plurality of bits. Each bit of the plurality of bits of the first memory is associated with a region of a second memory, and each bit indicates whether...  
WO/2019/133627A1
A touch control system comprising: a first electronic data processing device, a second electronic data processing device, and a tactile control surface, wherein the first electronic data processing device may be a computer, and the secon...  
WO/2019/133074A1
Steering logic circuitry includes bit-flipping logic that determines a first neighboring redundant word line adjacent to a redundant word line of a memory bank, which also includes normal word lines. Redundant word lines include main wor...  
WO/2019/125368A1
An apparatus is provided which comprises: a magnetic junction; and an interconnect adjacent to the magnetic junction, wherein the interconnect comprises a super lattice of a neutral and charged perovskite.  
WO/2019/124057A1
The present invention adjusts magnetization intensity using a chopping current so as to record magnetic data from which a favorable reproduction waveform can be obtained. This card reader 1 is provided with a writing magnetic head 6A. A ...  
WO/2019/120587A1
An ADC (50) is disclosed. It comprises a plurality of sub ADCs (A1-AM) configured to operate in a time-interleaved manner and a sampling circuit (60) configured to receive an analog input signal of the ADC (50), wherein the sampling circ...  
WO/2019/120592A1
Method and apparatus for processing a digital image file, comprising providing a digital image including image data for a plurality of pixels; detecting an area within the digital image; recording an identification of the detected area i...  
WO/2019/125560A1
Systems, apparatuses, and methods for performing efficient memory accesses in a computing system are disclosed. In various embodiments, a computing system includes computing resources and a memory controller coupled to a memory device. T...  
WO/2019/125507A1
A method to adaptively and dynamically set a bias scheme of a crossbar array for a write operation includes: performing a read-before-write operation to determine a number of cells n to be written during a write operation; comparing n to...  
WO/2019/125525A1
Memory devices (10) coupled to host devices may receive clocking signals and data strobe signals (DQS) during write operations, which may present a skew. Memory specifications may include Write Preambles, preambles in the data signal pro...  
WO/2019/121574A1
A computer implemented method of producing an audio track comprises: receiving at an input of a computer interface a request for a track; generating responsive to the request a set of audio production settings; determining from the reque...  
WO/2019/099737A3
Access to a networked communication session is provided to each of a plurality of user computing devices that are each configured with at least a camera, audio input subsystem, and audio output subsystem. During the networked communicati...  
WO/2019/125782A1
One example includes a memory circuit. The circuit includes a memory array arranged as rows and columns of memory cells. An array portion stores a respective memory word in a given one of the rows in response to a word-write signal corre...  
WO/2019/126064A1
A non-volatile memory device and methods for operating the same are provided. The memory device may have multiple complementary memory cells. The method of blank check includes detecting a state value of each of the true and complementar...  
WO/2019/120991A1
Method for activating a feature of a chip(10) having an interface (20) comprising at least two power pins (GND, VCC). The method comprises the following steps: -the chip measures a series of voltage values between said power pins, -the c...  
WO/2019/125795A1
The present disclosure includes apparatuses and methods for material implication operations in memory. An example apparatus may include a plurality of memory cells coupled to a first access line and a plurality of second access lines, an...  
WO/2019/126746A1
Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a certain number bits having a first logic state prior to storing the user data ...  
WO/2019/125572A1
A lapping tool assembly includes a mount tool and an interposer structure interposed between actuators and the mount tool, where the interposer includes interposer pins reactively coupled with the actuators such that each interposer pin ...  
WO/2019/125779A1
The present disclosure includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at lea...  
WO/2019/124287A1
An image recording method in an image processing apparatus, includes the steps of acquiring, from a plurality of cameras, respective video images which the plurality of cameras start capturing in the sea before a first light that is lit ...  
WO/2019/121150A1
An apparatus configured to: based on (i) captured spatial audio content of a scene comprising audio that is associated with information indicative of at least a direction in the scene from which said audio was captured; and (ii) visual f...  
WO/2019/125684A1
An apparatus is provided which comprises: an array of physically unclonable function (PUF) devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin or...  
WO/2019/125568A1
Techniques for reducing a downshift in the threshold voltage of a select gate transistor of a memory device. Due to an electric field in a NAND string, holes can move in a charge-trapping layer from a dummy memory cell to a select gate t...  
WO/2019/125523A1
A device (10) includes a signal input to receive a data input as part of a bit stream. The device (10) also includes a reference input to receive a reference signal. The device (10) further includes push circuitry (228) to receive a firs...  
WO/2019/123068A1
A method includes writing a data set to a sequential access medium. The method also includes reading the data set immediately after being written to the sequential access medium in a read-while-write process to identify one or more fault...  

Matches 151 - 200 out of 858,320