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Patent Searching and Data


Matches 151 - 200 out of 854,492

Document Document Title
WO/2018/059159A1
A shift register unit, a driving method, a gate driving circuit and a display apparatus. The shift register unit comprises: a clock control circuit (10), an output control circuit (20) and an output circuit (30). The shift register unit ...  
WO/2018/061405A1
The purpose of the present invention is to suppress damage to a substrate and improve a substrate processing efficiency. In order to achieve the purpose, a substrate processing apparatus is provided with: a processing tank that accommoda...  
WO/2018/062478A1
An objective of the present invention is to provide a magnetic powder for which the particle size distribution of epsilon-type iron oxide particles is narrow. Another objective of the present invention is to provide a magnetic powder sui...  
WO/2018/064424A1
Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board (PCB) that includes a printed circuit board defining a length and...  
WO/2018/062000A1
A card reader of the present invention comprises: an encrypting magnetic head 6 which encrypts a magnetic signal that is read from a card; and a main control unit which controls the entire device including the encrypting magnetic head 6....  
WO/2018/063861A1
Dynamic redundancy registers for use with a device are disclosed. The dynamic redundancy registers allow a memory bank of the device to be operated with high write error rate (WER). A first level redundancy register (el register) is coup...  
WO/2018/061710A1
The purpose of the present invention is to provide a magnetoresistive effect element (10) having a larger magnetoresistive effect. A magnetoresistive effect element according to the present invention comprises a substrate (11), a first f...  
WO/2018/063093A1
According to embodiments of the present invention, a memory device is provided. The memory device includes an electrochemical metallization memory (ECM) cell and a valence change memory (VCM) cell arranged one over the other. According t...  
WO/2018/063209A1
Substrates, assemblies, and techniques for enabling a resistive random access memory cell are disclosed herein. For example, in some embodiments, a device may include a source, where the source includes a source junction, a gate, and a d...  
WO/2018/063697A1
Memory refresh includes timing offsets for different memory devices, to initiate refresh of different memory devices at different times. A memory controller sends a refresh command to cause refresh of multiple memory devices. In response...  
WO/2018/063901A1
In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory array, the storage device to program, during a first programming pass, a plurality of cells of a first wordline of the NAND flash memory array to s...  
WO/2018/063446A1
A ReRAM cell array has rows and columns and includes first and second complementary bit lines for each row, a first, second and third word lines for each column and a source bit line for each row. A ReRAM cell at each row and column incl...  
WO/2018/061377A1
A playback device provided with: an optical system for dividing a cross-section of superimposed light into a plurality of regions in the tangential direction and/or the radial direction, using the plurality of superimposed light correspo...  
WO/2018/061995A1
A card reader 10 is provided with a peak detection unit 142 which detects a peak point of a reproduction signal from a digital signal in accordance with a threshold value, i.e. a determination level which is made to track the output of a...  
WO/2018/058331A1
The present invention relates to a method and apparatus for controlling volume, wherein same are used to realize automatic volume control, so that the output volume can make a user feel more comfortable. The method comprises: monitoring ...  
WO/2018/063292A1
A data storage system is described that uses wafer-level packaging. In one embodiment an apparatus includes a silicon wafer, a plurality of memory cells formed directly on the wafer, an encapsulant formed over the memory cells, a plurali...  
WO/2018/064188A1
An indirection mapping data structure can maintain a mapping between logical block addresses used by a host computer and physical data storage locations on a solid state drive. Changes to the indirection mapping data structure can be sto...  
WO/2018/060656A1
The invention relates to a supercapacitor comprising: an electrolyte having a first end and a second end opposite the first end; a first electrode (E1) in contact with the first end of the electrolyte; and a second electrode (E2) in cont...  
WO/2018/063741A1
Cache memory clock generation circuits for reducing power consumption and read errors in cache memory are provided. In one aspect, a cache memory clock generation circuit employs detector circuit configured to receive a way address and g...  
WO/2018/062189A1
The present invention addresses the problem of providing: an Ni-Ta system alloy which is free from composition unevenness and has improved mechanical strength, and wherein Ta compound phases are finely dispersed by adding a predetermined...  
WO/2018/061267A1
The present invention is provided with: a front surface plate 34 fixed to a hard disc drive (HDD) 30; and a cover 20 attached to the front surface plate 34. A cover 20 can slide in the taking out direction between a first position close ...  
WO/2018/064285A1
Systems and methods are described for providing an image validation module. The image validation mobile enables capture, enhancement, validation, and upload of a digital image to a networked computing service, applying criteria that corr...  
WO/2018/063570A1
Technologies for a physically unclonable function with magnetic tunnel junctions (MTJs) is disclosed. An MTJ may have a fixed layer and a free layer. The MTJ may have two stable states: one in which the orientation of the magnetization o...  
WO/2018/063177A1
The present disclosure relates to the fabrication of spin transfer torque memory devices, wherein a spin transfer torque element is connected to a PMOS transistor. In one embodiment, the spin transfer torque element may have a fixed side...  
WO/2018/063730A1
Aspects of the embodiments are directed to systems, methods, and devices for generating a design of experiments (DOE) matrix, the DOE matrix comprising a set of possible combinations of values for a plurality of electrical parameters; it...  
WO/2018/063916A1
Aspects disclosed herein relate to techniques and an efficient architecture for enabling multi-way reads on highly associative content addressable memory (CAM) arrays. For example, a method for performing a tag search of a tag array can ...  
WO/2018/063735A1
Integrated circuits may include dual mode memory cells. Dual mode memory cells may be operated in a lookup-table mode or a memory mode. A dual mode memory cell may have configuration ports for supporting a configuration operation and use...  
WO/2018/063308A1
A two transistor, one resistor gain cell and a suitable storage element are described. In some embodiments the gain cell has a resistive memory element coupled to a common node at one end to store a value and to a source line at another ...  
WO/2018/063164A1
Embodiments include a resistive random access memory (RRAM) memory cell which is the same as a RRAM storage cell. The RRAM storage cell has a resistive material layer and a semiconductor layer between two electrodes, where the semiconduc...  
WO/2018/063728A1
Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of inde...  
WO/2018/059204A1
An audio device, comprising a housing (101), a circuit board (102), a rotating shell (104), a contact switch (105), and a trigger (106); the circuit board (102) is disposed in the housing (101); the housing (101) is rotatably connected t...  
WO/2018/059093A1
A shift register unit, a gate scanning unit, a drive method and a display device. The shift register unit comprises: a reset module (300), configured to transmit, under control of a reset control signal input end, a signal of a signal co...  
WO/2018/056105A1
The present technique relates to an information processing apparatus, an information processing method, a program and an information processing system with which a schedule for recording programs listed in a search result can be easily s...  
WO/2018/057766A1
A method and related apparatus for using an indication of RRAM cell resistance to determine a write condition are disclosed. A cell characteristic of an RRAM cell is determined to a finer resolution than a data read value. A write condit...  
WO/2018/057226A1
An integrated circuit (IC), as a computation block of a neuromorphic system, includes a time step controller to activate a time step update signal for performing a time-multiplexed selection of a group of neuromorphic states to update. T...  
WO/2018/057429A1
A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory...  
WO/2018/057228A1
Provided are a method and apparatus for programming non-volatile memory using a multi-cell storage cell group to provide error location information for retention errors. Each storage cell in the non-volatile memory is programmed with thr...  
WO/2018/057460A1
Metal-oxide semiconductor (MOS) transistor offset-cancelling (OC), zero-sensing (ZS) dead zone, current-latched sense amplifiers (SAs) (CLSAs) (OCZS-SAs) for sensing differential voltages are provided. An OCZS-SA is configured to amplify...  
WO/2018/057137A1
Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes an input pad, an input buffer including a first input node and a second input node, a switch that couples the first input...  
WO/2018/055614A1
A method for detecting errors is performed on a data string which includes an information portion and a redundancy portion. The information portion includes two or more sub-strings. The method includes generating respective redundancy wo...  
WO/2018/057191A1
The embodiments herein describe technologies of initializing resistive memory devices (e.g., non-volatile and volatile memory devices). In one method, a first voltage is applied across a resistance change material of a memory cell to for...  
WO/2018/057400A1
Approaches, techniques, and mechanisms are disclosed for manufacturing and operating high density memory systems. The high density memory systems can increase the amount of memory available to a computing system by allowing the connectio...  
WO/2018/057014A1
Disclosed herein are asymmetric selectors for memory cells, and related devices and techniques. In some embodiments, a memory cell may include: a storage element; and a selector device coupled to the storage element, wherein the selector...  
WO/2018/055455A1
The technology relates to processing one or more audio streams. The processing may include segmenting the one or more audio streams into structural components comprising a tonal stream and a transient stream. The tonal stream and the tra...  
WO/2018/054222A1
A multiple disk loader apparatus includes a plurality of rods. Each rod has a pair of pins extending radially from a side of the rod. The pair of pins are spaced circumferentially around the rod with respect to each other. Each pin has a...  
WO/2018/055768A1
The number of selectable chips is increased without adding signal lines to a general-purpose memory controller. A semiconductor storage device is provided with: a memory controller; a plurality of memory chips; a selection unit connected...  
WO/2018/055733A1
This storage device comprises a first memory cell and a second memory cell adjacent to the first memory cell, and a sequencer which, when reading data from the first memory cell, performs a first read operation on the second memory cell,...  
WO/2018/057717A1
Certain exemplary embodiments can provide a system, machine, device, manufacture, circuit, composition of matter, and/or user interface adapted for and/or resulting from, and/or a method and/or machine-readable medium comprising machine-...  
WO/2018/055171A1
A method of erasing data using a file-based protocol from a data storage apparatus for repurposing, reallocation to a new user or retirement of the data storage apparatus, the data storage apparatus comprising a memory using a file-based...  
WO/2018/057896A1
Provided are a neuromorphic computing device, memory device, system, and method to maintain a spike history for neurons in a spiking neural network. A neural network spike history is generated in a memory device having an array of rows a...  

Matches 151 - 200 out of 854,492