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Patent Searching and Data


Matches 201 - 250 out of 857,132

Document Document Title
WO/2019/033647A1
The present invention is applied in the technical field of electronic communications, and provides an error correction method, apparatus and device for a flash memory, and a computer readable storage medium. The error correction method c...  
WO/2019/036072A1
Devices, systems, and methods include controls for on-die termination (ODT) and data strobe signals. For example, a command to de-assert ODT for a data pin (DQ) during the read operation. An input, such as a mode register, receives an in...  
WO/2019/036257A1
The present disclosure relates generally to the field of power supply wiring in a semiconductor device. In one embodiment, a semiconductor device is disclosed that includes, an uppermost metal layer including a power supply enhancing wir...  
WO/2019/036360A1
Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured...  
WO/2019/033599A1
The present application discloses a shift-register circuit used as a shift-register unit of current stage including a control sub-circuit coupled to a shift-register unit of previous stage and configured to recharge a pull-up node of the...  
WO/2019/033009A1
Systems and methods are disclosed for preparing and evolving atomic defects in diamond. Silicon vacancy spins may be cooled to temperatures equal to or below 500 mK to reduce the influence of phonons. The cooling, manipulation, and obser...  
WO/2019/031068A1
This base unit is provided with: a base unit chassis that supports a spindle motor; a heat dissipating member that dissipates heat to a base unit chassis side, on which a disc is not mounted, said heat having been generated from a stator...  
WO/2019/032249A1
A method for programming a ReRAM cell including a ReRAM device connected in series with an access transistor includes biasing the ReRAM cell with a programming potential that configures the access transistor in a common-source configurat...  
WO/2019/032327A1
Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify vertical alignment between data transmitted using multi-level signaling. Such multi-leve...  
WO/2019/032293A1
A driver of a multi-level signaling interface is provided. The driver may be configured reduce noise in a multi-level signal (e.g., a pulse amplitude modulation signal) generated by the driver using switching components of different pola...  
WO/2019/032562A1
The present disclosure includes apparatuses comprising replaceable memory. An example apparatus may include a controller and a memory package coupled to the controller and including a plurality of memory dies. At least one of the memory ...  
WO/2019/029494A1
The present application provides a mobile terminal, a memory and a record file editing method, said editing method comprising: entering a recording mode according to a starting instruction of a user; detecting environment sound sources a...  
WO/2019/032151A1
As described above, certain modes of operation, such as the Fast Zero mode and the ECS mode, may facilitate sequential access to individual cells of a memory array. To facilitate this functionality, a command controller may be provided, ...  
WO/2019/032407A1
In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and t...  
WO/2019/032328A1
A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled...  
WO/2019/030971A1
Provided is a spacer which is used in a magnetic disk device, the spacer: prevents the occurrence of vibration of a magnetic disk that is alternately layered with the spacer; exhibits little thermal expansion; has high precision; and exh...  
WO/2019/032271A1
Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without in...  
WO/2019/030500A1
Broadly speaking, embodiments of the present technique provide a 3D interconnected die stack for transferring a data signal between die structures, the stack comprising on a first die structure a transmitter comprising a synchronising sp...  
WO/2019/032270A1
Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify peak-to-peak voltage differences between the amplitudes of data transmitted using multi-...  
WO/2019/032329A1
A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in ...  
WO/2019/032455A1
Data bit inversion tracking in cache memory to reduce data bits written for write operations is disclosed. In one aspect, a cache memory including a cache controller and a cache array is provided. The cache array includes one or more cac...  
WO/2019/031226A1
This spin current magnetoresistive effect element is provided with: a magnetoresistive effect element; a spin orbit torque wire which extends in a first direction intersecting a stacked direction of the magnetoresistive effect element, a...  
WO/2019/032206A1
An optical data-recording system comprises a laser, a dynamic digital hologram, an electronic controller, and a scanning mechanism. The dynamic digital hologram includes a plurality of holographic zones, and is configured to direct the i...  
WO/2019/027727A1
An example apparatus comprises a first portion of an array of memory cells, a second portion of the array of memory cells, a first register corresponding to the first portion, and a second register corresponding to the second portion. Th...  
WO/2019/027741A1
Apparatuses for receiving an input data signal are described. An example apparatus includes: a plurality of data input circuits and an internal data strobe generator. Each data input circuit of the plurality of data input circuits includ...  
WO/2019/026720A1
[Problem] To provide a polarization beam splitter that can have reduced size and weight relative to the prior art. [Solution] This polarization beam splitter has a translucent substrate and a hologram layer provided on the front surface ...  
WO/2019/027938A1
Techniques for verifying a magnetic tape are disclosed. The techniques include obtaining a position signal generated by reading a magnetic tape using a stationary tape head. Next, a simulated current for adjusting a position of the tape ...  
WO/2019/024481A1
A shifting register and a driving method therefor, a grid driving circuit, and a display device, which belong to the technical field of displaying. The shifting register comprises: a forward scanning input sub-circuit (1) for pre-chargin...  
WO/2019/027576A1
A hermetically-sealed container for one or more data storage devices may include a first container part or base including a planar main portion, a plurality of sidewalls extending from the main portion, and a plurality of diffusion lengt...  
WO/2019/027719A1
The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a data pattern in a group of resistance variable memory cells corresponding to a...  
WO/2019/025896A1
Improved spin hall MRAM designs are provided that enable writing of all of the bits along a given word line together using a separate spin hall wire for each MTJ. In one aspect, a magnetic memory cell includes: a spin hall wire exclusive...  
WO/2019/026474A1
A submount (100) comprises a substrate (110), the substrate (110) having: a first surface (101); a second surface (102) that is substantially perpendicular to the first surface (101); a third surface (103) that is substantially perpendic...  
WO/2019/028335A1
An interleaved DAC configured to generate a set of second digital inputs responsive to a set of first digital inputs. Each second digital input is obtained by subtracting the other second digital inputs in the set from the corresponding ...  
WO/2019/027862A1
Utilizing the topological character of patterns in 3D structures is beneficial for information storage, magnetic memory and logic systems. One embodiment describes the use of topological knots, exemplified by a Möbius strip, in which a ...  
WO/2019/027544A1
In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto refresh mode. A significa...  
WO/2019/026197A1
Disclosed is a semiconductor storage device such as a DRAM or the like wherein, in order to solve a row hammer problem, a row control circuit is provided which latches, as a victim address by a prescribed row address latch method, a targ...  
WO/2019/027937A1
Techniques for performing precise tracking in optical tapes are provided. The techniques include providing and using a servo pattern on an optical tape. The servo pattern includes a first set of parallel physical grooves slanted in a fir...  
WO/2019/027805A1
Various embodiments, disclosed herein, include apparatus and methods to provide separate regulated voltages to an electronic device. Multiple voltage regulators can be provided with phase alignment circuitry coupled to the multiple volta...  
WO/2019/027916A1
Various embodiments include apparatus and methods having a data receiver with a real time clock decoding decision feedback equalizer. In various embodiments, a digital decision feedback loop can be implemented in a data receiver circuit,...  
WO/2019/027799A1
Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibrat...  
WO/2019/023000A1
A superconducting bidirectional current driver (10) is disclosed. The current driver includes a first direction superconducting latch that is activated in response to a first activation signal and a second direction superconducting latch...  
WO/2019/022811A1
Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a dummy memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, ...  
WO/2019/021078A1
The present disclose concerns an apparatus (5) for generating a magnetic field (60) comprising a plurality of permanent magnets (51, 52) arranged in a plane, each magnet (51, 52) being spatially separated along the plane from the adjacen...  
WO/2019/022837A1
Disclosed are techniques for minimizing performance degradation due to refresh operations in a dynamic volatile memory sub-system. In an aspect, a refresh scheduler coupled to the dynamic volatile memory sub-system generates a batch memo...  
WO/2019/019608A1
A shift register circuit, a scan driving circuit, an array substrate and a display apparatus. The shift register circuit has an input end (IN) and an output end (OUT), and comprises: an input module (11), which is respectively connected ...  
WO/2019/023042A1
Methods, systems, and devices for varying a filter capacitance are described. Within a memory device, voltages may be applied to access lines associated with two voltage sources to increase the capacitance provided by the access lines be...  
WO/2019/021368A1
A conductive section (10) electrically connected to a bracket (2) has electric resistivity that is smaller than that of the bracket (2) and that of a navigation chassis (3), and conducts a noise current to a connecting section (7) via a ...  
WO/2019/019550A1
Disclosed in the present invention are a self-adaptive LDPC code error correction code system and method applied to a flash memory. The system and method can improve the error correction capability of the error correction code in the fla...  
WO/2019/021498A1
This semiconductor storage device includes: a first memory string that includes a first memory cell; a bit line; a sense amplifier that includes a latch circuit; a data register that is connected to the sense amplifier and that transmits...  
WO/2019/022732A1
Embedded non-volatile memory structures having bilayer selector elements are described. In an example, a memory device includes a wordline. A bilayer selector element is above the wordline. The bilayer selector element includes a ferroel...  

Matches 201 - 250 out of 857,132