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Patent Searching and Data


Matches 201 - 250 out of 857,683

Document Document Title
WO/2019/066821A1
Described is an apparatus which comprises: a storage node; a first device coupled to the storage node; a second device coupled to a first reference and the storage node, wherein the second device has negative differential resistance (NDR...  
WO/2019/062245A1
Disclosed are a shift register and driving method therefor, a gate driver circuit, and a display device. The shift register comprises an input circuit, a reset circuit, a first control circuit, a first output circuit, and a second output...  
WO/2019/065345A1
In order to assign an index used for cueing when recorded data is reproduced, and to carry out said assignment onsite by means of a simple operation during the recording of sound or the recording of an image and at an arbitrary timing de...  
WO/2019/062265A1
A shift register unit, a gate driving circuit and driving method, and a display device. The shift register unit comprises: a first input circuit (10), used for outputting the voltage of a first voltage terminal (V1) to a pull-up node (PU...  
WO/2019/066906A1
A 2T-2S SRAM cell exhibiting a complementary scheme, that includes two selector devices that exhibit negative differential resistance. Advantages include lower area and better performance than traditional SRAM cells, according to some em...  
WO/2019/064111A1
The invention is notably directed to a resistive memory device comprising a control unit for controlling the resistive memory device and a plurality of memory cells. The plurality of memory cells includes a first terminal, a second termi...  
WO/2019/067886A1
A storage controller is provided. The storage controller includes a host interface, a media interface, and a processing system. The processing system is configured to receive data from the host system, select write locations within the s...  
WO/2019/064963A1
A rack for a disc storage device comprises: a housing space surrounded by right and left side plates and top and bottom partition plates and accommodating a disc storage device; a guide part provided on the side plates and fitted to a gu...  
WO/2019/061965A1
A shift temporary storage circuit (20) and a display panel using same. The shift temporary storage circuit (20) comprises multi stages of shift registers, each shift register comprising: a first switch (T10), one control end (101a) of th...  
WO/2019/067053A1
A device (10) includes a decoder (204, 365) configured to receive an input signal. The decoder (204, 365) is configured to also output a control signal based on the input signal. The device (10) further includes an equalizer (202, 292, 3...  
WO/2019/067980A1
Provided herein is a computing memory architecture. The non-volatile memory architecture can comprise a resistive random access memory array comprising multiple sets of bitlines and multiple wordlines, a first data interface for receivin...  
WO/2019/067262A1
Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes voltage regulators in an integrated circuit device, and a frequency control block and a module included in the integrated circuit...  
WO/2019/067251A1
Various embodiments can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits...  
WO/2019/065200A1
Provided is a magnetic tape which comprises, on a non-magnetic supporting body, a magnetic layer that contains a ferromagnetic powder and a binder, and which is configured such that: the magnetic layer contains an oxide polishing agent; ...  
WO/2019/065199A1
Provided is a magnetic tape which comprises, on a non-magnetic supporting body, a magnetic layer that contains a ferromagnetic powder and a binder, and which is configured such that: the magnetic layer contains an oxide polishing agent; ...  
WO/2019/058820A1
This sputtering target contains, as a metal component, Co and one or more metals selected from the group consisting of Cr and Ru, and the molar ratio of the content of the one or more metals selected from the group consisting of Cr and R...  
WO/2019/059970A1
Technology is described for identifying non-volatile memory cells having data that should be refreshed. The technology could be used to identify which groups of memory cells that store cold data should have a data refresh. In one aspect,...  
WO/2019/058209A1
A calibration system for media content comprises a memory, a media device, a plurality of different types of sensors, and a control circuitry. The memory is configured to store a media item and expected-emotions-tagging metadata for the ...  
WO/2019/060083A1
Systems, methods, and apparatus for writing data into a static random access memory (SRAM) are provided. A write driver circuit includes a bitcell array, a bitline coupled to the bitcell array, and a first driving circuit configured to d...  
WO/2019/056803A1
A shift register unit (100), a gate drive circuit (10), a display device (1), and a drive method. The shift register unit (100) comprises an input circuit (110), a pull-up node reset circuit (120), an output circuit (130) and a coupling ...  
WO/2019/058819A1
This sputtering target contains Co and Pt as metal components, and the molar ratio of the Pt content to the Co content is 5/100 to 45/100. The sputtering target also contains Nb2O5 as a metal oxide component.  
WO/2019/059951A1
An apparatus is provided which comprises: a magnetic junction; a first layer exhibiting spin orbit coupling properties, wherein the first layer is adjacent to the magnetic junction, wherein the first layer includes a first side and a sec...  
WO/2019/060191A1
An electronic device includes a pressure-sensitive user interface component, a memory device, and a processor. The memory device stores executable instructions to perform a method that displays a media player on a display of the electron...  
WO/2019/060067A1
Disclosed are methods and apparatus for implementing a memory controller, such as a bus integrated memory controller (BIMC) that includes a memory built-in-self-test (MBIST) controller or logic. The MBIST controller is configured for tes...  
WO/2019/060121A1
In an example, a method of memory repair may include receiving, by a memory repair unit, a plurality of memory identifiers. The method may include determining, by the memory repair unit, that a first memory identifier of the plurality of...  
WO/2019/060019A1
A device (10) includes one or more memory banks (12) configured to store data. The device (10) also includes a data receiver (62) configured to receive distorted input data as part of a data stream, apply a correction factor to the disto...  
WO/2019/056935A1
Provided are an FT4222-based testing system and method for an SPI flash. The testing method comprises: invoking an FT4222 chip device from debugging tools according to a testing statement inputted by a tester; configuring testing conditi...  
WO/2019/059313A1
[Problem] To display information regarding performers in a program at, for example, the bottom of a television display while the program data is being played back. [Solution] The present invention is provided with: a recording medium for...  
WO/2019/059022A1
The present technology pertains to a reproduction device, a reproduction method, a program, and a recording medium, in which display at the start of reproduction of an HDR video stream can be made stable. In a case where: reproducible co...  
WO/2019/056833A1
Provided are a shift register unit, scan driving circuit, array substrate, and display device, said shift register unit comprising: an input circuit (11), used for setting a first node (PU) to a valid level when an input terminal (IN) is...  
WO/2019/056282A1
A mobile hard disk capable of displaying storage capacity and a working method therefor. The mobile hard disk comprises a housing (1), a USB data interface (2) is provided on a side face of the housing (1), and a hard disk motherboard (3...  
WO/2019/060868A1
A system for cleaning a media transport device includes a cleaning substrate sized and configured to fit within at least a portion of a media travel pathway of the transport device. The cleaning substrate includes scarifying holes that s...  
WO/2019/060573A1
A method of detecting random telegraph noise defects in a memory includes initializing a first bit cell of the memory to a first value and reading the first value from the first bit cell. The method also includes writing a second value t...  
WO/2019/060120A1
In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may change a device operating voltage from a first voltage to a second voltage while the assist circuit is in a first stat...  
WO/2019/059591A1
A semiconductor memory device is disclosed. The semiconductor memory device comprises: a first circuit unit including a third PMOS transistor and a first inverter, which includes a first NMOS transistor and a first PMOS transistor; a sec...  
WO/2019/055182A1
A memory array with memory cells arranged in rows and columns. Each memory cell includes source and drain regions with a channel region there between, a floating gate disposed over a first channel region portion, and a second gate dispos...  
WO/2019/051861A1
A mixed flash memory read/write method and a mixed read/write flash memory. In the mixed flash memory read/write method, operations of the following four storage modes are mixed: single-level storage, multi-level storage, triple-level st...  
WO/2019/054495A1
The purpose of the present invention is to provide a memory circuit device that enables the circuit to be downscaled. The memory circuit device is provided with: multiple memory cells 11, each comprising a variable resistance memory comp...  
WO/2019/054434A1
A failure sign detection device 40 is provided with: an issuing unit 41 that issues an access request for inspection of a storage device 50 at a prescribed first timing, and also at a second timing later than the first timing; a collecti...  
WO/2019/025864A3
The present disclosure includes distributed processors and methods for compiling code for executed by the distributed processors. In one implementation, a distributed processor may include a substrate; a memory array disposed on the subs...  
WO/2019/052061A1
A low-power consumption dual in-line memory, and an enhanced driving method therefor. The memory has a pluggable dual in-line structure and is compatible with a DDR internal memory interface. The memory has the following pin assignment b...  
WO/2019/055179A1
This disclosure provides systems, methods, and apparatus, including computer programs encoded on computer storage media, for network communication when recording audio and video (A/V) of a subject. In one aspect, a device may determine o...  
WO/2019/055935A1
A dynamic error introduced by track-and-hold circuits can be reduced by using an input signal derivative to perform linear extrapolation during the hold period, allowing the output of the track-and-hold circuit to provide improved perfor...  
WO/2019/055105A1
A memory device that includes a plurality of memory cells arranged in rows and columns, a plurality of bit lines each connected to one of the columns of memory cells, and a plurality of differential sense amplifiers each having first and...  
WO/2019/054001A1
A nonvolatile storage device according to the present invention is provided with: a variable resistance element (10) comprising a first electrode (2), a second electrode (4), and a variable resistance layer (3) the resistance value of wh...  
WO/2019/054148A1
A fluorine-containing ether compound which is represented by R1-R2-CH2-R3-CH2-R4-R5. (In the formula, R3 represents a perfluoropolyether chain; each of R1 and R5 independently represents an optionally substituted alkyl group, an organic ...  
WO/2019/055827A1
Disclosed are systems, devices, and processes to create a successful and effective personal video commercial through the use of one or more scripts, timecode commands, storyboarding, teleprompting displays, analyzers directed to static d...  
WO/2019/053917A1
A brightness characteristic generation method including: a first determination step (S32) for determining, for each of a plurality of frames constituting a moving image, a value obtained by dividing the number of pixels, among a pluralit...  
WO/2019/055074A1
A spin orbit torque magnetoresistive random access memory (SOT MRAM) cell includes a magnetic tunnel junction that contains a free layer having two bi-stable magnetization directions, a reference magnetic layer having a fixed magnetizati...  
WO/2019/049686A1
A combining weight coefficient used in neural network computation is stored in a memory array (20), a word line (22) corresponding to the input data of a neural network is driven by a word line drive circuit (24), and a bit line to which...  

Matches 201 - 250 out of 857,683