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Patent Searching and Data


Matches 201 - 250 out of 853,211

Document Document Title
WO/2017/163884A1
Provided is a magnetic head with which a decrease in read accuracy due to noise can be suppressed. The magnetic head 6 comprises: a head body 22 that includes a core 32 having a gap 31, and a coil 34 wound around the core 32; a demodulat...  
WO/2017/165272A1
Systems and methods are provided to record portions of media assets. User request is received to record a media asset together with a criterion for recording portions of that media asset. A content recognition algorithm is executed again...  
WO/2017/165823A1
A media content item sequencing system determines a sequence for playback of selected media content items, such as media content items in a playlist. The system calculates similarities between all possible pairs of the media content item...  
WO/2017/161678A1
A shift register, a drive method thereof, a gate drive circuit and a display apparatus. The shift register comprises a pull-up drive unit (11), a pull-up unit (12), a pull-down unit (13), a pull-down drive unit (14) and a reset unit (15)...  
WO/2017/164970A1
Two vertical NAND strings can share a common bit line by providing two pairs of drain select transistors. Channels of each vertical NAND string containing an adjoining pair of drain select transistors are incorporated into a respective v...  
WO/2017/162222A1
The invention relates to a method for producing an electrochemical accumulator, characterized by the following steps: a) providing a non-conductive substrate; b) mounting a first conductor track made of conductive material on the substra...  
WO/2017/165012A1
One embodiment describes a superconducting cell array logic circuit system. The system includes a plurality of superconducting cells arranged in an array of at least one row and at least one column. The superconducting cell array logic c...  
WO/2017/158517A1
A magnetoresistive-based signal shaping circuit (100) for audio applications comprising: a field emitting device (4) configured for receiving an input current signal (41) from an audio signal source and for generating a magnetic field (4...  
WO/2017/160311A1
Damascene-based approaches for embedding spin hall MTJ devices into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including a metallization layer. The logic proce...  
WO/2017/160230A1
A write device for magnetic media, a method of writing a magnetic media, and a HAMR head structure are provided, the device comprising a write component configured to heat a first portion of a magnetic media; at least one additional heat...  
WO/2017/158466A1
To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and ...  
WO/2017/161103A1
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may maintain a digit line voltage at a ground reference for a duration associated with biasing a ferroelectric capacitor of a...  
WO/2017/160710A1
System, method, and computer product embodiments for efficiently casting interactively- controlled visual content displayed on a first display screen to a second display screen. In an embodiment, the computing device sends the visual con...  
WO/2017/160414A1
Described is an apparatus which comprises: a bit-line (BL) read port; a first local bit-line (LBL) coupled to the BL read port; a second LBL; and one or more clipper devices coupled to the first and second LBLs. The apparatus allows for ...  
WO/2017/159313A1
Provided is an information processing apparatus including: circuitry configured to execute a data reproduction process and a decoding of reproduction control information associated with subtitle data defined by an extensible markup langu...  
WO/2017/158620A1
Apparatus for sustaining magnetic oscillations using a magnonic crystal cavity Embodiments herein provide an apparatus for controlling Spin Waves (SWs). The apparatus includes a magnetic film substrate. Further the apparatus includes one...  
WO/2017/160553A3
A memory device includes a semiconductor layer with an in-plane polarization component switchable between a first direction and a second direction. A writing electrode is employed to apply a writing voltage to the semiconductor layer to ...  
WO/2017/158465A1
Provided is a storage device in which power consumption is reduced. This storage device has a plurality of memory cells, a precharge circuit, a latch circuit, a pair of bit lines, and a pair of local bit lines. The precharge circuit has ...  
WO/2017/161020A1
Apparatuses, systems, methods, and computer program products are disclosed for data register (280) copying for a non-volatile storage array (200). An apparatus may include an array of non-volatile storage cells (200). A set of write buff...  
WO/2017/159561A1
This information recording medium (100) includes at least three information layers (10, 20, 30). The information recording medium (100) has, in one information layer (10, 20, 30), a second dielectric film (13, 23, 33) including ZrO and I...  
WO/2017/161102A1
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory cell of a first memory cell array or a second memory cell of a second memory...  
WO/2017/160286A1
In some examples, a method of controlling a transition between a functional mode and a test mode of a logic chip includes enabling a clock input of a disable circuit in response to an indication that the logic chip is in the functional m...  
WO/2017/157110A1
A method of controlling high-speed access to a double data rate (DDR) synchronous dynamic random access memory (SDRAM), and a device. The method comprises: dividing, according to a dynamic allocation strategy, a DDR SDRAM into variable b...  
WO/2017/159432A1
This magnetic memory is provided with: a plurality of magnetoresistance effect elements including a first ferromagnetic metal layer with a fixed magnetization direction, a second ferromagnetic metal layer configured to have a variable ma...  
WO/2017/161083A1
A method of implementing fault tolerance in computer memory includes translating a logical address to a first physical address for a first memory location in the computer memory. The computer memory includes redundant memory locations. A...  
WO/2017/159186A1
A recording device (5) comprises a reception unit, a recording unit (53), a first selection unit, and a second selection unit. The reception unit is connected to a vehicle exterior image capture device (2) and a vehicle interior image ca...  
WO/2017/156909A1
A shift register, a gate drive circuit and a display panel. In the shift register, a first node control module 11 provides a signal of an input signal end (Input) for a first node A under the control of a first clock signal end (CK1), an...  
WO/2017/156850A1
A shift register and a drive method therefor, a gate drive circuit, an array substrate and a display device. The shift register (10) comprises: a pull-up control module (1), a pull-up module (2), a pull-down control module (3), a pull-do...  
WO/2017/159560A1
This information recording medium includes at least three information layers. At least one of the information layers has a second dielectric film, a recording film, and a third dielectric film, provided in that order from the side irradi...  
WO/2017/160893A1
A switching device, comprising an anti-ferromagnet structure having an upper layer and a lower layer, the upper layer and lower layer anti-ferromagnetically coupled by an exchange coupling layer, the upper and lower layer formed of a sim...  
WO/2017/159471A1
An optical phase difference member 100 is provided with a transparent substrate 40 on which a pattern 80 of recesses and protrusions is formed, a covering layer 30 covering recesses 70 and projections 60 in the pattern 80 of recesses and...  
WO/2017/155662A1
Systems, methods, and computer programs are disclosed for allocating memory in a hybrid parallel/serial memory system. One method comprises configuring a memory address map for a multi-rank memory system with a dedicated serial access re...  
WO/2017/154403A1
A fluorine-containing ether compound which is represented by formula (1). R1-R2-CH2-R3-CH2-R4 (1) (In formula (1), R1 represents a terminal group which contains an organic group having at least one double bond or triple bond; R2 represen...  
WO/2017/152392A1
A method and apparatus for refreshing a flash memory device, achieving optimization of refresh operations for flash memories. The method comprises: a memory controller (112) reading first data from a first flash block (S402) and determin...  
WO/2017/154382A1
The purpose of the present invention is to accurately retrieve data in a storage device equipped with a variable-resistance cell. When a reference cell circuit receives an initialization signal exceeding a prescribed inversion threshold,...  
WO/2017/155749A1
There is provided a method comprising: causing received image and/or audio data associated with an audio-visual call to be played-out via a user interface; receiving, during the audio-visual call, an instruction to store received image a...  
WO/2017/155668A1
A method is provided that includes forming a vertical bit line (LBL11) disposed in a first direction above a substrate (502), forming a word line (WL10) disposed in a second direction above the substrate, the second direction perpendicul...  
WO/2017/152534A1
A method and device for acquiring an on-die termination (ODT) parameter of a double data rate (DDR) synchronous dynamic random access memory. The method comprises: arranging the m-th value of a DDR ODT and the n-th value of a column addr...  
WO/2017/155510A1
Described is an apparatus which comprises: an interconnect including a stack of metal layers having a first non-alloy metal adjacent to a metal and a first templating layer. The first non-alloy metal is formed of a material which is sele...  
WO/2017/155781A1
Apparatuses and methods are provided for logic/memory devices. An example apparatus comprises a plurality of memory components adjacent to and coupled to one another. A logic component is coupled to the plurality of memory components. At...  
WO/2017/155814A2
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be selected using a selection component that is in electronic communication with a sense amplifier and a ferr...  
WO/2017/154724A1
A recording data processing method in which, for each of an N number (N being a natural number of at least 3) of recording data pairs comprising two successive pieces of recording data when an N number of pieces of recording data are arr...  
WO/2017/155544A1
Examples herein relate to hardware accelerators for calculating node values of neural networks. An example hardware accelerator may include a crossbar array programmed to calculate node values of a neural network and a current comparator...  
WO/2017/154863A1
A regulator circuit (101) has a first stopped state, a second stopped state and an operating state, and includes: a detecting circuit portion (11) which detects the magnitude of an output voltage from the regulator circuit (101) and outp...  
WO/2017/154741A1
Through the present invention, a thin film including a FePt-based alloy usable as a magnetic recording medium can be independently formed, and the quantity of particles can be further reduced. A FePt-C-based sputtering target containing ...  
WO/2017/155508A1
Approaches for integrating spin torque transfer magnetic random access memory (STT-MRAM) memory arrays into a logic processor, and the resulting structures, are described. In an example, a logic processor including a logic region includi...  
WO/2017/153572A1
The present invention provides a computer-implemented method and an apparatus for manufacturing an analogue audio storage medium wherein digital audio data is converted into topographical data representing an analogue translation of the ...  
WO/2017/156444A1
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Offsets in the threshold voltage of switching components (e.g., transistors) connected to digit lines may be compensated by using various ope...  
WO/2017/155509A1
Described is an apparatus which input and output magnets, each configured to have six stable magnetic states including zero state, first state, second state, third state, fourth state, and fifth state, wherein the zero state is to point ...  
WO/2017/153604A1
CAM memory cell (100) comprising: a latch (103) comprising N first TFETs (102) that are connected in series between two supply potentials so that each source and drain of the first TFETs is connected either to one of the potentials or to...  

Matches 201 - 250 out of 853,211