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Patent Searching and Data


Matches 201 - 250 out of 861,271

Document Document Title
WO/2020/133199A1
A memory device comprises a memory array including memory cells, a temperature sensing circuit, and a memory control unit operatively coupled to the memory array. The memory control unit includes a processor. The processor is configured ...  
WO/2020/133276A1
A GOA unit and a GOA circuit thereof, and a display device. The GOA unit comprises a pull-up control module (110), a starting module (120), a pull-down and maintenance module (130), and a bootstrap capacitor (C1); wherein an output end o...  
WO/2020/132848A1
A storage array includes multiple wordlines of storage cells that can be selectively charged to an erase voltage or an inhibit voltage. Control logic associated with the storage array can perform erase verify in stages. On a first erase ...  
WO/2020/139422A1
An apparatus includes an address bus configured to convey a command address; a primary address latch connected to the address bus and configured to latch a first address; a primary counter connected to the primary address latch and confi...  
WO/2020/139534A1
Apparatuses and methods related to implementing a non-persistent unlock state for secure memory. Implementing the non-persistent unlock state can include verifying whether an access command is authorized to access a protected region of a...  
WO/2020/134034A1
A test system (100) for a memory card. The test system (100) comprises: a first circuit board (110), one side of which is provided with a plurality of contact groups (111) spaced apart from each other along the row direction, and the oth...  
WO/2020/136267A1
The present invention relates to an electronic device (10), comprising an input (12) and an output (14), the device (10) generating an output voltage when the input of the device (10) is supplied, the device (10) comprising: - a conversi...  
WO/2020/133202A1
A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is co...  
WO/2020/139460A1
A bootstrapped switch circuit includes an auxiliary loop circuit for assisting the boosting of a bootstrap voltage in a main loop circuit having a bootstrapped switch transistor. The boosted bootstrap voltage switches on the bootstrapped...  
WO/2020/139895A1
In some embodiments, an in-memory-computing SRAM macro based on capacitive- coupling computing (C3) (which is referred to herein as "C3SRAM") is provided. In some embodiments, a C3SRAM macro can support array-level fully parallel computa...  
WO/2020/094808A4
The invention relates to a method for producing a component, a component produced according to such a method, and a measurement system in which an information area of the component is encoded/marked by means of deformation.  
WO/2020/133630A1
Disclosed are a control method for a timing control chip of a display panel and a display panel. The control method comprises: outputting a write protection level to a write protection pin; detecting an actual level of the write protecti...  
WO/2020/139615A1
A method can include applying a first voltage to a first memory cell to activate the first memory cell, applying a second voltage to a second memory cell coupled in series with the first memory cell to activate the second memory cell so ...  
WO/2020/136394A2  
WO/2020/136141A1
Embodiments of the invention provide a memory device (100) comprising a memory (1) comprising at least one chip (2), each chip (2) comprising one or more banks (10) for storing a plurality of bits, each bank (10) comprising a set of rows...  
WO/2020/137341A1
Provided is a nonvolatile logic circuit that uses the non-complementarity of a pair of variable-resistance memory elements to achieve enhanced functionality without an increase in circuit scale. A nonvolatile logic circuit (10) that comp...  
WO/2020/137030A1
A lifter mechanism (16) has: a first lifter (44) that supports an arm (24) from underneath, and moves up and down between a first lower limit position and a first upper limit position; a second lifter (48) that supports the first lifter ...  
WO/2020/139519A1
Systems and methods for confirming the presence of a person or asset for a given purpose, and recording this information in a distributed ledger. The distributed ledger records and confirms presence indicia in connection with a transacti...  
WO/2020/132950A1
A drive circuit, comprising a first group of drive circuits (110) and a second group of drive circuits (120), the first group of drive circuits (110) and the second group of drive circuits (120) respectively comprising multiple levels of...  
WO/2020/139423A1
Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performi...  
WO/2020/139700A1
Methods, systems, and devices for detection of illegal commands are described. A memory device, such as a dynamic random access memory (DRAM), may receive a command from a device, such as a host device, to perform an access operation on ...  
WO/2020/134572A1
Disclosed in embodiments of the present application are a memory built-in self-test (MBIST) circuit and a test method for a memory, for use in reducing the development costs of modifying an MBIST circuit-supported test algorithm. The MBI...  
WO/2020/134036A1
A test board (10) and a test device. The test board (10) is used for testing a memory card, and comprises a circuit board (11) and a plurality of test circuits (12) disposed on the circuit board (11) and independent from each other, each...  
WO/2020/139424A1
A first memory die including an array of first memory stack structures and a logic die including a complementary metal oxide semiconductor (CMOS) circuit are bonded. The CMOS circuit includes a first peripheral circuitry electrically cou...  
WO/2020/131495A2
Systems and methods are disclosed herein for continuing playback of a digital tutorial until a user interrupts the playback by signaling to the system that there is an issue or that the user needs help. In some embodiments, the system de...  
WO/2020/125309A1
The present disclosure relates to a storage device with multiple storage crystal grains and an identification method therefor. The present disclosure uses different suppliers. With regard to a dynamic random access memory of the same waf...  
WO/2020/132255A2
Systems and methods are described herein for displaying subjects of a portion of content. Media data of content is analyzed during playback, and a number of audio signatures and/or action signatures are identified. Each signature is asso...  
WO/2020/131667A1
Systems, apparatuses and methods for organizing bits in a memory device are described. In a number of embodiments, an apparatus can include an array of memory cells, a data interface, a multiplexer coupled between the array of memory cel...  
WO/2020/131167A1
Techniques for reducing read disturb of memory cells in a two-tier stack having a lower tier and an upper tier separated by an interface. In a read operation, the channels of NAND strings are discharged before reading the selected memory...  
WO/2020/131893A2
A method of fabricating a magnetic storage device includes depositing a first conductive material. The method further includes electrically isolating distinct instances of the first conductive material to form a first wire extending alon...  
WO/2020/132438A1
Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier ...  
WO/2020/126269A1
The present invention relates to a CCD photodetector and an associated method for operation. In particular, the invention relates to a CCD photodetector for LiDAR systems, comprising a shift register (100) with a plurality of register ce...  
WO/2020/131528A1
A memory controller integrated circuit includes a clock signal generator circuit configured to generate a plurality of strobe signals. The memory controller integrated circuit further includes a memory interface circuit coupled to the cl...  
WO/2020/131457A1
Memory devices and methods of operating memory devices in which maintenance operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., operations in excess of a predetermined threshold) warrants a m...  
WO/2020/132432A1
Methods, systems, and devices related to content-addressable memory for signal development caching are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier a...  
WO/2020/128517A1
Provided herein are methods of encoding data on a polymer. Also provided are methods of reading data encoded on a polymer. Also provided are systems for encoding data on a polymer; systems for reading data encoded on a polymer; and data ...  
WO/2020/131265A1
Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read proces...  
WO/2020/129532A1
A semiconductor storage device according to one embodiment of the present invention comprises a substrate; a first storage element that is formed on the substrate and includes a first insulation film; and a second storage element that is...  
WO/2020/131196A1
An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, ...  
WO/2020/132152A1
2D heterostructures comprising Bi2Se3/MoS2, Bi2Se3/MoSe2, Bi2Se3/WS2, Bi2Se3/MoSe2. 2xS2x, or mixtures thereof in which oxygen is intercalated between the layers at selected positions provide high density storage devices, sensors, and di...  
WO/2020/128676A1
The present invention provides a semiconductor device with a new structure. This semiconductor device includes: a first transistor in which one of the source and the drain is electrically connected to a first interconnect for reading dat...  
WO/2020/124535A1
A method for operating an electronic device (1) comprises a processing unit (11), a video output (13) and an audio output (14), the method is characterized in that it comprises: playing (a0) an audiovisual content on the electronic devic...  
WO/2020/132435A1
Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier ...  
WO/2020/132428A1
Methods, systems, and devices related to signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a ...  
WO/2020/131868A1
A computing device includes one or more processors, a first random access memory (RAM) comprising magnetic random access memory (MRAM), a second random access memory of a type distinct from MRAM, and a non-transitory computer-readable st...  
WO/2020/132591A1
Described herein are embodiments related to holdup self-tests in memory sub-systems for power loss operations. A processing device receives a request to perform a holdup selftest to detect a defect in a holdup circuit that powers the pro...  
WO/2019/236117A3
Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a memory device can asynchronously indicate to a connected host that information in a mode register has been changed, obviating th...  
WO/2020/131168A1
Techniques for reducing read disturb of memory cells in a two-tier stack having a lower tier and an upper tier separated by an interface. In a read operation, the channels of NAND strings are discharged before reading the selected memory...  
WO/2020/131381A1
Embodiments of the disclosure are drawn to apparatuses and methods for timing refresh operations in a memory device. An apparatus may include an oscillator that provides a periodic signal to one or more refresh timer circuits. Each of th...  
WO/2020/124376A1
A shift register, comprising: a blanking input circuit (120), N shift register circuits (130_1 ... 130_N), and a compensation selection circuit (110), wherein the blanking input circuit (120) is configured to store a blanking input signa...  

Matches 201 - 250 out of 861,271