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JPH09162751A |
To reduce circuit scale by sharing a serial/parallel(S/P) converting circuit for the parallel conversion of serial input data and the serial conversion of parallel correction data. A full adder logic circuit 1 is composed of an adder cir...
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JPH09162750A |
To simplify the development of a program for signal conversion between a parallel signal and a serial signal. A communication conversion unit 5 is provided between a 1st equipment 30 inputting/outputting digital data as a parallel signal...
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JPH09153889A |
To provide a serialigation-parallelization converting circuit for a high speed digital signal. This serialization-parallelization converting circuit includes a transmitter(TX) and a receiver(RX) on one integrated circuit chip(IC). The tr...
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JPH09153821A |
To eliminate the exchange of a signal between super-high speed P/S converting ICs and to prevent a malfunction by executing parallel/serial conversion by means of two steps. 1ch10-bit signals 1-1 to 1-10 are inputted to a latch 4-1 so as...
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JPH09148939A |
To provide the radio communication equipment which more improves the communication quality according as transmitting voice or data at a higher speed and consequently transmits voice or data at a higher speed with the same communication q...
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JPH09135237A |
To improve the availability of a buffer by using both buffers respectively exclusive for transmission and reception as buffers for transmission/reception at the time other than loop back operation. At the time of normal transmission, MPU...
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JPH09130267A |
To prepare the main signal train of a bit array in a correct order by adjusting reception side clocks so as to be synchronized with transmission side clocks in the serial-parallel/parallel-serial conversion of transmission signals. In a ...
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JPH09130268A |
To select and switch a system without hit when asynchronous serial signals are inputted from duplexed serial transmission lines. The output signals of the serial transmission lines S0 and S1 are converted to parallel signals by serial-pa...
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JP2597732B2 |
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JPH0993131A |
To output each data by inputting directly the video stream of the MPEG2 system, a program stream and a transport stream to the decoder. A serial interface signal of compression video data by n-channels inputted to an input terminal 1 is ...
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JPH0993141A |
To attain serial/parallel conversion by converting plural serial data received with a clock signal into plural parallel data and outputting superimposingly sequentially by providing a time difference to parallel data. The conversion circ...
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JPH0983379A |
To make analog quantity, which is increased with the increase of a pulse density modulation(PDM) code, completely proportional to a PDM code No., by composing a PD modulator of a PDM circuit and a duty adjusting circuit. This device is p...
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JP2593200B2 |
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JP2593017B2 |
PURPOSE: To synchronously transfer serial data in order by controlling a counting operation based on a word signal and a clock pulse and determining the shift timing of a conversion circuit. CONSTITUTION: A detection circuit 11 outputs a...
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JPH0974433A |
To obtain an improved data form conversion circuit, OAM fault management cell extract circuit and frame length fault detection circuit in which the circuit scale can be reduced. In the circuit converting, e.g. an 8-bit parallel signal or...
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JPH09502579A |
PCT No. PCT/CA94/00377 Sec. 371 Date Mar. 11, 1996 Sec. 102(e) Date Mar. 11, 1996 PCT Filed Jul. 13, 1994 PCT Pub. No. WO95/02951 PCT Pub. Date Jan. 26, 1995A time division switching matrix capable of effecting rate conversion comprises ...
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JPH0961498A |
To realize a semiconductor IC circuit which can check a SAMPLE mode function of a boundary scan register without preparing a test pattern with an internal logic circuit. A boundary scan register comprises a selector 1 to select either on...
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JP2586804B2 |
PURPOSE: To perform redundancy switching of data in a system for which high reliability is requested without losing the data. CONSTITUTION: The data loss detection part 40 of an address control part 4 monitors the counting up of addresse...
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JP2584205B2 |
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JPH0955667A |
To operate a multiplexer normally by providing a variable delay circuit connecting to a control circuit to a data input side of a retiming use D-FF at a final output stage in the multiplexer so as to adjust each timing. A 1st stage of a ...
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JPH0955760A |
To efficiently transmit data between terminals in branch LANs belonging to different trunk LANs. Transmitted frames of the trunk LANs are converted by series/ parallel converters 23a and 23b into parallel transmitted frames, which are pa...
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JPH0934684A |
To provide a format conversion circuit which is small in circuit scale and does not require more numbers of wiring, in a frame format conversion circuit. This circuit is composed of a serial/parallel conversion means 5 inputting serial d...
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JPH0936823A |
To make a serial signal to be transmitted into the signal that an mBnB code is multiplexed for every word and to completely exhibit the mark ratio improving effect that the code is intrinsically provided. The encoding circuits 11 to 14 o...
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JP2572734B2 |
PURPOSE:To display the initial bit of a serial data to the final stage of a display device at any time by adopting the 2nd clock sufficiently shorter than the 1st clock and counting the 2nd clock till the content reaches the setting valu...
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JP2571457B2 |
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JP2570268B2 |
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JP2569498B2 |
PURPOSE:To realize a serial/parallel or a parallel/serial conversion FF with an integrated circuit of a few gate number and a small area by using a transfer gate in place of a selector gate. CONSTITUTION:The titled circuit is provided wi...
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JPH08340259A |
PURPOSE: To turn a selector to a parallel/serial conversion circuit capable of a high-speed operation by performing control so that the time period of selecting one input terminal is included in the time period in which an input signal v...
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JP2565768B2 |
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JP2565144B2 |
PURPOSE: To provide a high-speed, highly integrated and low-power serial/ parallel converter capable of being used as a bidirectional shift register as well by transferring data based on a second clock whose phase is opposite to a first ...
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JPH08335930A |
PURPOSE: To provide a communication equipment and a communication method by which error is corrected at a low cost simply in the case of correcting error through the use of a BCH code. CONSTITUTION: A header of 15-bit is added to transmi...
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JPH08327700A |
PURPOSE: To obtain a PCM codec, and s test method therefor, in which the output data from an A/D (analog/digital) conversion output section can be tested in a short time. CONSTITUTION: A PCM codec is provided, at the A/D conversion outpu...
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JPH08328819A |
PURPOSE: To accurately convert desired parallel data to serial data by inactivating a load signal based on a command signal while the command signal which holds the parallel data is being inputted to the parallel-serial conversion means ...
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JP2562716B2 |
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JPH08316850A |
PURPOSE: To convert a speed of parallel data simultaneously altogether even in the case of data of plural channels by arranging once data entered in irregular timings. CONSTITUTION: In the serial parallel data conversion method receiving...
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JP2552102B2 |
PURPOSE: To separately execute the operation of the formatting/deformatting of digital data from a digital signal processor, and to decrease a required time and the consumption of a power at the time of the formatting/deformatting, relat...
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JPH08288862A |
PURPOSE: To provide the arrangement conversion circuit for data in an I interface where the circuit constitution can be made small-scale and simple. CONSTITUTION: A data arrangement conversion circuit consists of a first data arrangement...
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JP2545817B2 |
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JPH08265168A |
PURPOSE: To increase number of bits of a parallel output without increasing the circuit scale by generating a load-enable-signal after the input of the least significant bit of input data on the basis of serial input data and a clock sig...
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JPH08265170A |
PURPOSE: To materialize the circuit technology suitable for circuit integration by using a synchronizing signal and a signal synchronously with the synchronization of one line of a received serial data string so as to regulate the shift ...
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JP2542606B2 |
A serial-to-parallel converter receiving a clock signal and continuous serial stream of input data, each having TTL logic levels, produces parallel outputs for driving current switches of a digital-to-analog converter (DAC). The data and...
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JP2541883B2 |
PURPOSE:To reduce the number of control lines. CONSTITUTION:A clock and strobe generating circuit 3 is provided which generates a shift-in clock S9 for data to a shift register 1 and a strobe S7 for data transfer from the shift register ...
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JP2542802B2 |
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JP2536135B2 |
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JPH08237141A |
PURPOSE: To facilitate observation fo serial data output in the case of test and to easily revise test serial input data in the serial-parallel converter. CONSTITUTION: A data selection circuit 1 selecting an input of a reception shift r...
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JPH08237140A |
PURPOSE: To build up a shift circuit with a high operating frequency by arranging input output terminals for two DFF circuits each having a latch function in axial symmetry and arranging plural sets of the circuits while the length of wi...
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JPH08237142A |
To convert parallel data to serial data without using a high frequency clock by using a phase locked loop to generate a clock which has the same frequency as an original system clock but a phase different from that of the original system...
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JPH08228157A |
PURPOSE: To provide the data transfer circuit for which it is not necessary to reset fixed data. CONSTITUTION: This circuit is provided with the parallel fixed data, switch circuit 35 for selectively outputting the parallel input data, s...
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JPH08223146A |
PURPOSE: To provide the parallel data transposing circuit which has a lower circuit redundancy suitable for the case that the parallel data transposing method is limited to cyclic bit shift in the parallel data transposing circuit which ...
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JPH08223085A |
PURPOSE: To realize switching from the current system to the standby system without short break by equalizing data strings, frame phases, and stuffing phases in the radio transmission equipment in the not standby system provided with at ...
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